HMC7043LP7FE datasheet(20/44 Pages) AD

20 / 44 page

Data Sheet

HMC7043

Rev. B | Page 19 of 43

Table 10. Basic Divider Controls

Bit Name

Description

Channel Enable

Channel enable. If set to 0, the channel is disabled. If set to 1, the channel can be enabled depending on the

settings of the Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode bits.

12-Bit Channel Divider[11:0]

Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider

(Output Mux Selection[1:0] = 2 or 3)

High Performance Mode

High performance mode. Adjusts the divider and buffer bias to improve swing/phase noise slightly at the expense of

power. The performance advantage is about 1 dB, and the current penalty depends on whether the divider is enabled.

Coarse Digital Delay[4:0]

Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the clock input. This circuit is

practically noiseless; however, note that a low amount of additional current is consumed.

Fine Analog Delay[4:0]

Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] = 1

to expose this channel. Exposing this channel causes phase noise degradation of up to 12 dB; therefore, do not use

on noise sensitive DCLK channels.

Output Mux Selection[1:0]

Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input clock.

Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output Mux

Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and degrades

phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic skew vs. a path

that is divider-based. Such skew can be compensated for with delay (digital and analog) on the divider-based

path.

Force Mute[1]

Force mute. If 1, and the channel enable is true (channel enable = 1) and Force Mute[0] = 0, the signal just

before the output buffer is asynchronously forced to Logic 0. To see the effect of this, the output buffer must

be enabled, which is dependent on the dynamic driver enable and Start-Up Mode[1:0] controls.

Table 11. Channel Features

Bit Name

Description

Slip Enable

Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated

following a recognized SYNC or pulse generator startup).

SYNC Enable

SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via

the SYSREF FSM) to reset the phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without

risking the state of the divider.

Start-Up Mode[1:0]

00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC

enable = 1.

11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF

controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the

pulse generator chain. This mode is only supported for divide ratios > 31.

Table 12. Pulse Generator Mode Behavior Options

Bit Name

Description

Dynamic Driver Enable

Dynamic output buffer enable (pulse generator mode only).

0 = the output buffer is simply enabled/disabled with the main channel enable.

1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power

down outside pulse generator events.

Force Mute[0]

Idle at Logic 0 (pulse generator mode only).

1 = if the buffer remains on outside of the pulse generator chain, drive to Logic 0.

0 = if the buffer remains on outside of the pulse generator chain, allow the outputs to float naturally to

approximately VCM.

HMC7043LP7FE Datasheet(PDF) 20 Page - Analog Devices

HMC7043LP7FE Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL