HMC7043

Data Sheet

Rev. B | Page 26 of 43

Table 18. Supply Network of the HMC7043 by Pin for the Clock Output Network

Per Output Channel

Comment

Typical Current (mA)

0

1

2

3

4

Digital Regulator and Other Sources

2.5

0.5

2.5

2.5

2.5

2.5

Buffer

LVPECL

Including term currents

43

43

43

43

CML100

High Power

Including term currents

31

Low Power

24

LVDS

High Power

At 307 MHz

10

10

Low Power

8

CMOS

At 100 MHz, both sections

25

Channel Mux

Different Power Modes Deleted

2

2

2

2

Digital Delay

Off

Setpoint > 1

3

3

3

Analog Delay

Off

0

Minimum Setting

Glitchless mode enabled

9

9

Maximum Setting

9

9

Divider Logic

0

Not using divider path

0

0

÷1

27

÷2

24

÷3

31

÷4

28

÷5

30

÷6

26

÷8

28

÷16

29

29

÷32

29

÷2044

29

29

4

4

Subtotal

2.5

48

87

13

89

1

Profile 0 is sleep mode; Profile 1 is fundamental mode; Profile 2 is SYSREF channel matched to fundamental mode; Profile 3 is LVDS—high power signal source from

other channel; and Profile 4 is worst case configuration for power consumption of a channel.

2

The base current consumption of the circuit (for example, mux) is included in the buffer typical current.

3

Currents only occur temporarily during a synchronization event.