MB95650L datasheet(63/105 Pages) CYPRESS

63 / 105 page

Document Number: 002-04696 Rev. *A

Page 63 of 105

MB95650L Series

(Continued)

(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min

Typ

Max

Clock frequency

FCL

X0A, X1A

—

32.768

—

kHz

When the suboscillation circuit is

used

—

32.768

—

kHz When the sub-external clock is used

FCRL

—

100

150

kHz When the sub-CR clock is used

Clock cycle time

tHCYL

X0, X1

—

61.5

—

1000

When the main oscillation circuit is

used

—

30.8

—

1000

When an external clock is used

X0, X1

—

250

—

When the main PLL clock is used

tLCYL

X0A, X1A

—

30.5

—

µs

When the subclock is used

Input clock

pulse width

tWH1, tWL1

—

12.4

—

When an external clock is used, the

duty ratio should range between

40% and 60%.

X0, X1

—

125

—

When the main PLL clock is used

tWH2, tWL2 X0A

—

15.2

—

µs

When an external clock is used, the

duty ratio should range between

40% and 60%.

Input clock

rising time and

falling time

tCR, tCF X0, X0A

—

When an external clock is used

CR oscillation

start time

tCRHWK

—

µs

When the main CR clock is used

tCRLWK

—

µs

When the sub-CR clock is used

PLL oscillation

start time

tMCRPLLWK

——

—

100

µs

When the main CR PLL clock is

used

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