MB95650L datasheet(74/105 Pages) CYPRESS

74 / 105 page

Document Number: 002-04696 Rev. *A

Page 74 of 105

MB95650L Series

Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.

(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)

*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the

serial clock.

*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.

*3: See “18.4.2. Source Clock/Machine Clock” for tMCLK.

Parameter

Symbol

Pin name

Condition

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCK

Internal clock operation

output pin:

CL = 80 pF  1 TTL

5 tMCLK*3

—ns

SCK

  SOT delay time

tSHOVI

SCK, SOT

50

50

Valid SIN

 SCK

tIVSLI

SCK, SIN

tMCLK*3  80

—

SCK

 valid SIN hold time

tSLIXI

SCK, SIN

—

Serial clock “H” pulse width

tSHSL

SCK

External clock operation

output pin:

CL = 80 pF  1 TTL

3 tMCLK*3 tR

—ns

Serial clock “L” pulse width

tSLSH

SCK

tMCLK*3  10

—

SCK

  SOT delay time

tSHOVE SCK, SOT

—

2 tMCLK*3  60

Valid SIN

 SCK

tIVSLE

SCK, SIN

—

SCK

 valid SIN hold time

tSLIXE

SCK, SIN

tMCLK*3  30

—

SCK fall time

SCK

—

SCK rise time

SCK

—

MB95650L Datasheet(PDF) 74 Page - Cypress Semiconductor

MB95650L Datasheet(HTML) 74 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL