MB95650L datasheet(81/105 Pages) CYPRESS

81 / 105 page

Document Number: 002-04696 Rev. *A

Page 81 of 105

MB95650L Series

18.4.8 I2C Bus Interface Timing

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)

*1: R represents the pull-up resistor of the SCL0/1 and SDA0/1 lines, and C the load capacitor of the SCL0/1 and SDA0/1 lines.

*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal

at “L” (tLOW) does not extend.

*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT  250 ns is

fulfilled.

Parameter

Symbol

Pin name

Condition

Value

Unit

Standard-mode

Fast-mode

Min

Max

Min

Max

SCL clock frequency

fSCL

SCL0, SCL1

R = 1.7 k

,

C = 50 pF*1

100

400

kHz

(Repeated) START condition hold time

SDA

 SCL 

tHD;STA

SCL0, SCL1,

SDA0, SDA1

4.0

—

0.6

—

µs

SCL clock “L” width

tLOW

SCL0, SCL1

4.7

—

1.3

—

µs

SCL clock “H” width

tHIGH

SCL0, SCL1

4.0

—

0.6

—

µs

(Repeated) START condition setup time

SCL

 SDA 

tSU;STA

SCL0, SCL1,

SDA0, SDA1

4.7

—

0.6

—

µs

Data hold time

SCL

 SDA 

tHD;DAT

SCL0, SCL1,

SDA0, SDA1

03.45*2

00.9*3

µs

Data setup time

SDA

 SCL 

tSU;DAT

SCL0, SCL1,

SDA0, SDA1

0.25

—

0.1

—

µs

STOP condition setup time

SCL

  SDA 

tSU;STO

SCL0, SCL1,

SDA0, SDA1

4—

0.6

—

µs

Bus free time between STOP condition and

START condition

tBUF

SCL0, SCL1,

SDA0, SDA1

4.7

—

1.3

—

µs

SDA0,

SDA1

SCL0,

SCL1

tWAKEUP

tHD;STA

tSU;DAT

fSCL

tHD;STA

tSU;STA

tLOW

tHD;DAT

tHIGH

tSU;STO

tBUF

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