MB95650L datasheet(76/105 Pages) CYPRESS

76 / 105 page

Document Number: 002-04696 Rev. *A

Page 76 of 105

MB95650L Series

Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.

(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)

*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the

serial clock.

*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.

*3: See “18.4.2. Source Clock/Machine Clock” for tMCLK.

Parameter

Symbol

Pin name

Condition

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCK

Internal clock operation

output pin:

CL = 80 pF  1 TTL

5 tMCLK*3

—ns

SCK

 SOT delay time

tSHOVI

SCK, SOT

50

50

Valid SIN

 SCK

tIVSLI

SCK, SIN

tMCLK*3  80

—

SCK

 valid SIN hold time

tSLIXI

SCK, SIN

—

SOT

 SCKdelay time

tSOVLI

SCK, SOT

3tMCLK*3 70

—

0.8 VCC

0.2 VCC

tSHOVI

tSOVLI

tIVSLI

tSLIXI

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SCK

SOT

SIN

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

tSCYC

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