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MB95650L Datasheet(PDF) 68 Page - Cypress Semiconductor |
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MB95650L Datasheet(HTML) 68 Page - Cypress Semiconductor |
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68 / 105 page  Document Number: 002-04696 Rev. *A Page 68 of 105 MB95650L Series FCH (Main oscillation clock) Divided by 2 Divided by 2 Divided by 2 FCRH (Main CR clock) FMCRPLL (Main CR PLL clock) FCL (Suboscillation clock) FCRL (Sub-CR clock) FMPLL (Main PLL clock) SCLK (Source clock) MCLK (Machine clock) Machine clock divide ratio select bits (SYCC:DIV[1:0]) Clock mode select bits (SYCC:SCS[2:0]) Division circuit × × × × 1 1/4 1/8 1/16 Schematic diagram of the clock generation block A/D converter operation range 5.5 3 MHz 16 kHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.8 1.5 0.0 ≈ Operating voltage - Operating frequency (TA = 40 °C to 85 °C) |
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