SPL10A1

7

The block diagram is shown as below:

2

TONE

DRIVER

MIX

ENVE LOPE

DA

AUD

PITCH

Timer Carry

speech

Melody

Tone

„ LIQUID CRYSTAL DISPLAY

The SPL10A1 can directly drive the liquid crystal display (LCD) panel of 1/2 duty, 1/3 duty,

and 1/4 duty with 1/2 bias or 1/3 bias. It has 4 commons and 32 segments signal pins. In

share mode (Timer/Counter is used), the LCD being refresh by LCDL interrupt. The INT

routine will read the number of common which is under serving, and send the next

common's pattern to LCD port ($10 - $13) from RAM buffer. If the Timer/the Counter is

not used, hardware mechanism will auto refresh the LCD after writing OPTION register

($1F).

The power connections for LCD (1/2 bias,1/3bias) are shown as below:

VDD2

0.1u

1 / 2 Bias

VDD1

1 / 3 Bias

VDD2

CUP2

CUP1

0.01u

VDD

0.01u

0.01u