Data Sheet

HMC8200LP5ME

Rev. B | Page 21 of 25

Digital Gain Amplifier: DGA Control

Table 7. Digital Gain Amplifier (Address 0x03)

Bit No.

Bit Name

Description

Reset

Access

15

Reserved

Not used

0x0

R/W

[14:9]

DGA_CTRL

Override SPI FIL2_FRQ_SET and use 8-bit word from OTP

0x0

R/W

0 = minimum gain

1 = …

100011 = maximum gain

[8:0]

Reserved

Not used

0x0

R/W

Digital Gain Amplifier: Amplifier Current, Envelope Level, and VGA Attenuation Bias

Table 8. Digital Gain Amplifier, (Address 0x04)

Bit No.

Bit Name

Description

Reset

Access

[15:9]

Reserved

Not used

0000111

R/W

[8:7]

AMP_CUR

Amplifier current

11

R/W

[6:2]

ENV_LVL

Envelope level

11100

R/W

[1:0]

VGA_ATT_BIAS

VGA attenuation bias

10

R/W

Image Reject Mixer: Sideband, and Polarity and Offset for I

Table 9. Image Reject Mixer Register, (Address 0x05)

Bit No.

Bit Name

Description

Reset

Access

[15:12]

Reserved

Reserved

0010

Logic 0010 for normal operation

11

IRM_IS

Image sideband

1

R/W

0 = upper sideband

1 = lower sideband

[10:9]

Reserved

Reserved

01

R/W

Logic 01 for normal operation

8

OFFSET_POLARITY_I

Offset Polarity I

0

R/W

[7:0]

IRM_OFFSET_I

Image reject mixer offset for I

0x0

R/W

Image Reject Mixer: Polarity and Offset for Q

Table 10. Image Reject Mixer Register, (Address 0x06)

Bit No.

Bit Name

Description

Reset

Access

[15:9]

Reserved

Not used

1111000

R/W

8

OFFSET_POLARITY_Q

Offset Polarity Q

0

R/W

[7:0]

IRM_OFFSET_Q

Image reject mixer offset for Q

0x0

R/W