WM8776 datasheet(15/55 Pages) WOLFSON

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WM8776

PP Rev 1.91 June 2004

Table 8 shows the settings for ADCRATE and DACRATE for common sample rates and

ADCMCLK/DACMCLK frequencies.

System Clock Frequency (MHz)

128fs

192fs

256fs

384fs

512fs

768fs

SAMPLING

RATE

(DACLRC/

ADCLRC)

DACRATE

=000

DACRATE

=001

ADCRATE/

DACRATE

=010

ADCRATE/

DACRATE

=011

ADCRATE/

DACRATE

=100

ADCRATE/

DACRATE

=101

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.144

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

Unavailable

192kHz

24.576

36.864

Unavailable

Table 8 Master Mode ADC/DACLRC Frequency Selection

ADCBCLK and DACBCLK are also generated by the WM8776. The frequency of ADCBCLK

and DACBCLK depends on the mode of operation.

In 128/192fs modes (DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes

(ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is

selected as the audio interface mode then BCLK=MCLK. Note that DSP mode cannot be

used in 128fs mode for word lengths greater than 16 bits or in 192fs mode for word lengths

greater than 24 bits.

ZERO DETECT

The WM8776 has a zero detect circuit for each DAC channel, which detects when 1024

consecutive zero samples have been input. The two zero flag outputs (ZFLAGL and

ZFLAGR) may be programmed to output the zero detect signals (see Table 9) that may then

be used to control external muting circuits. A ‘1’ on ZFLAGL or ZFLAGR indicates a zero

detect. The zero detect may also be used to automatically enable the PGA mute by setting

IZD. The zero flag output may be disabled by setting DZFM to 00. The zero flag signal for

each DAC channel will only be enabled if it is enabled as an input to the output summing

stage.

DZFM[1:0]

ZFLAGL

ZFLAGR

Zero flag disabled

Left channel zero

Right channel zero

Both channel zero

Either channels zero

Either channel zero

Table 9 Zero Flag Output Select

POWERDOWN MODES

The WM8776 has powerdown control bits allowing specific parts of the WM8776 to be

powered off when not being used. The 5-channel input source selector and input buffer may

be powered down using control bit AINPD. When AINPD is set all inputs to the source

selector (AIN1l/R to AIN5L/R) are switched to a buffered VMIDADC. Control bit ADCPD

powers off the ADC and also the ADC input PGAs. The stereo DAC has a separate

powerdown control bit, DACPD allowing the DAC and analogue output mixer to be powered

off when not in use. This also switches the analogue outputs VOUTL/R to VMIDDAC to

maintain a dc level on the output.

Setting AINPD, ADCPD and DACPD will powerdown everything except the references

VMIDADC, ADCREF and VMIDDAC. These may be powered down by setting PDWN.

Setting PDWN will override all other powerdown control bits. It is recommended that AINPD,

HPPD, ADCPD and DACPD are set before setting PDWN. The default is for all blocks to be

enabled other than HPPD.

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