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• 1 Channel Mode B: This mode uses a sensor tied to the Blue

OS input only. Illumination is switched in RGBRGB pattern at

the line rate. Each color has own digital offset and gain coeffi-

cients as well as static Gain and Offset data. Note that there is

a one line delay between when a line is exposed to a color and

when pixels of that color are clocked out of the sensor. For

example, the Green LEDs should be on while you are clocking

out Red pixels. This mode typically uses Illumination Mode 2.

4.4 External SRAM Interface

The external 8 bit SRAM is used for line buffering and coefficient

data. For 300 dpi, 16kbytes (2729 pixels * 16 bits/pixel * 3 colors

= 16kbytes) are used for offset and gain coefficients. For 600 dpi,

32Kbytes (5460 pixels * 16 bits/pixel * 3 colors = 32kbytes) are

used for offset and gain coefficients. The rest is used for the cir-

cular image data buffer.

The LM9830 supports three SRAM sizes: 64K, 128K, and 256K.

The 64K mode uses addresses A0-A15. To allow two 32k x 8

SRAMs to function as one 64k x 8 SRAM, address bit A16 is the

inverse of address bit A15. This allows A15 and A16 to be used

as CS pins for the two 32k x 8 SRAMs. The 64K mode is only rec-

ommended for use with 300dpi optical sensors. 64K (32K coeffi-

cients/32K image data buffer) is not enough SRAM for 600dpi

sensors.

The 128K mode uses addresses A0-A16. To allow two 64k x 8

SRAMs to function as one 128k x 8 SRAM, address bit A17 is the

inverse of address bit A16. This allows A16 and A17 to be used

as CS pins for the two 64k x 8 SRAMs.

The 256K mode uses addresses A0-A17.

There are 4 SRAM access modes: 8 bit/4 slot, 8bit/8 slot, 12 bit/4

slot (half duplex 12 bit), 12 bit/8 slot (full duplex 12 bit). The 4 slot

modes are lower bandwidth and can be used with slower SRAM,

while the 8 slot modes provide higher system performance.

Figure 42 indicates the relative bandwidth used in each mode.

The ADC and the first stage of the digital processing block always

run at the pixel rate, which is 1/8 of the MCLK frequency. The off-

set correction data and the gain correction coefficient data must

be provided at the pixel rate.

In the 8 bit/4 slot mode, each 8 bit correction data RAM access

takes 2 MCLKs. The 8 bit write from the pixel processing block

takes 2 MCLKs. 8 bit reads from SRAM to the host also take 2

MCLKs. Note that in this mode, the maximum rate pixel data can

be stored in SRAM is also the maximum rate pixel data can be

read and transmitted to the host. In configurations where the host

I/O can not constantly receive data at the pixel rate, the SRAM

buffer may fill up even if the host is capable of burst reads at rates

much greater than the pixel rate.

To reduce or eliminate buffer full conditions, there is a higher

bandwidth 8 bit/8 slot mode where all RAM read accesses take 1

MCLK cycle. In this mode there are 4 slots where data can be

read and sent to the host, allowing the buffer to be emptied up to

4 times faster than it is being filled. Combined with an intelligent

scanner driver routine, this mode will reduce or eliminate the

number of times a scanner has to stop during a scan.

This mode

is only guaranteed to work when the MCLK frequency is 25MHz

or lower.

To calibrate the scanner, or to actually scan an image and send

the raw 12 bit data back to the PC, additional modes are required

to transmit the 12 bit pixel data through the 8 bit interface. The 12

bit/4 slot (or half duplex) mode does this by storing the 12 bit data

as a high byte (the 4 MSBs of the 12 bit word) and a low byte (the

8 LSBs of the 12 bit word). The timing is similar to the 8 bit/4 slot

scenario, except that the slot normally allocated to sending data

to the host is now given to writing the second half of the 12 bit

word to SRAM.

In this mode you can not transmit data to the host

while scanning. To read the data out of RAM, you must either

write to the command register to stop scanning (this is typically

how it would be done during calibration), or wait until the buffer

fills up (how it would typically be done during a raw 12 bit image

Figure 40: 1 Channel Mode A

G LED

B LED

R LED

COEF.

DATA

SC = selected channel (=green in this example)

Figure 41: 1 Channel Mode B

G LED

B LED

R LED

COEF.

DATA

Figure 42: SRAM Access Modes

MCLK

123

56781

8 bit/

4slot

8 bit/

8slot

12 bit/ 4slot

(Scanning)

12 bit/

8slot

R1: Offset Coefficient read

R2: Gain Coefficient read

R3: 8 bit pixel data read (to host)

R4: 12 bit pixel data read, MSB (to host)

R5: 12 bit pixel data read, LSB (to host)

W1: 8 bit Pixel Data Write

W2: 12 bit pixel data write, MSB

W3: 12 bit pixel data write, LSB

R1 R2

R4 R5

12 bit/ 4slot

(Reading)

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