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LM9830 Datasheet(PDF) 43 Page - National Semiconductor (TI) |
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LM9830 Datasheet(HTML) 43 Page - National Semiconductor (TI) |
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43 / 45 page ![]() +24V + – Reset A A Phase A Invert Set-Dominant S/R Flipflop +24V B B Stepper Phase A Stepper Phase A Stepper Phase B Stepper Phase B DAC code for phase A 3 SENSE1 SENSE2 HIGH CURRENT GND SENSE 1 Ω 1 Ω DAC A: 0.125V, 0.191V, 0.353V, 0.462V, 0.500V Comparators need no hysteresis. SR flipflops are set periodi- cally by pulse from PWM Generator. Flipflops can only be reset after SR goes low when Reset (comparator output) is high (VSENSE > VDAC). Reset is level sensitive, not edge sensitive. ÷4 ÷1 to 256 8 ÷64 PWM Generator 0/64 to 63/64 high time 6 CR CR + – Reset Set-Dominant S/R Flipflop 3 DAC A: 0.125V, 0.191V, 0.353V, 0.462V, 0.500V Set Set CRYSTAL IN (50MHz) Optional zener speeds up motor current decay when transistor is off. VZ ~ 24V DAC code for phase B A A Q Q Phase B Invert B B TriState Stepper Motor Outputs CR CR CR LM9830 Stepper Motor Current Controller Block Diagram |
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