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6.5 Returning to Transparency Mode with LM9830 Reset

The host can return the LM9830 to Transparency Mode and reset

the LM9830 by taking the INIT, AUTOFEED, SELECT_IN, and

STROBE pins low and then high again. Approximately 2 - 3

MCLKs after the rising edge of INIT, the LATCH pin will go high,

the TRISTATE pin will go low, and the LM9830 will tristate its D0-

D7 and control line outputs. This will reset the LM9830 as well as

make it transparent.

6.6 Writing to the Configuration Register (Parallel Port)

The timing for writing to the LM9830 (sending data from the PC to

the LM9830) is shown in Figure 53. This is EPP timing, and it is

used for all parallel port Writes, even when in Nibble Mode (Nib-

ble Mode is only used to send data from the peripheral to the

host).

The write consists of two cycles, an address write cycle that tells

the LM9830 which address is going to be written to, and a data

write cycle that transmits the data to be stored in that address.

The handshaking is as follows:

• The host takes STROBE low, indicating that the next operation

is a write.

• The host puts data on D0-D7.

• The host takes SELECT IN low to indicate that the data is valid.

• The LM9830 latches the data and indicates that the data has

been latched by taking BUSY high.

• The host responds and brings SELECT IN and STROBE high.

• The LM9830 responds to the rising edge of SELECT IN by tak-

ing BUSY low.

This completes the address write cycle. The LM9830 is now pre-

pared for a byte write to the location contained in the address

byte. The handshaking for the data write is basically identical,

except AUTOFEED is used to latch the data instead of SELECT.

To write large quantities of data to a particular address, the

address only has to be written once. All data write operations will

write to the last address written. This is useful for writing DataPort

(register 06) data.

6.7 Reading From The Configuration Register (Parallel Port)

The procedure for reading the configuration register is different

for the EPP and Nibble Modes.

6.7.1 EPP Mode Configuration Register Read

An EPP read is shown in Figure 54. The handshaking for the

address write cycle of a read is identical to the address cycle for a

write. The data read cycle is as follows:

• The host maintains STROBE high, indicating that the next oper-

ation is a read.

• The host tristates D0-D7

• The host takes AUTOFEED low to request data from the

LM9830.

• The LM9830 places the data on the bus.

• The LM9830 takes BUSY high to indicate the data is valid.

• The host latches the data and responds by taking AUTOFEED

high.

• The LM9830 tristates the bus.

• The LM9830 takes BUSY low to indicate the cycle is complete

and it is ready for another cycle.

To read large quantities of data from a particular address, the

address only has to be written once. All data read operations will

read from the last address written. This is useful for reading pixel

(register 00) and DataPort (register 06) data.

6.7.2 Nibble Mode Configuration Register Read

This is not the traditional application of “Nibble Mode”, it is more

efficient and lower cost variation. The first half of the cycle is an

EPP address write, followed by a Nibble Mode read. Also, BUSY

is used for handshaking and ACK for a databit, eliminating the

problems caused by the hardware inversion of BUSY on the PC,

as well as allowing BUSY to perform roughly the same function it

does in EPP mode.

STROBE

AUTOFEED

INIT

Figure 51: LM9830 Transparent without Reset

SELECT IN

STROBE

AUTOFEED

INIT

Figure 52: LM9830 Transparent with Reset

SELECT IN

STROBE

AUTOFEED

BUSY

Addr

D0 - D7

Figure 53: Writing to the Configuration Register

8-Bit Data

SELECT IN

8-Bit Data

STROBE

AUTOFEED

BUSY

Addr

D0 - D7

Figure 54: Reading from the Configuration Register (EPP)

SELECT IN

LM9830 Datasheet(PDF) 35 Page - National Semiconductor (TI)

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