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MTV030 Revision 1.0 10/15/1999

MTV030

MYSON

TECHNOLOGY

tents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2

and Table 3 for detail description of this operation.

HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is,

the pixels' number per H line equal to HORR*12. It is recommended that HORR should be greater

than or equal to 36 and smaller than 150M / (Hfreq*12). The initial value is 40 after power up.

RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will

be appended below each display row, and the maximum space is 31 lines. The initial value is 0

after power up.

OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.

BSEN - Enable the bordering and shadowing effect.

SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise

the bordering is chosen.

FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state

or vice verca.

BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blending-in/blending-out

function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly

takes about 0.5 second to fully display the whole menu or to disappear completely.

WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after

power up.

RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set

to "1". The initial value is 0 after power up.

FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the

displaying of characters or windows, otherwise, it outputs high only during the displaying of charac-

ter.

TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,

while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are

in high impedance state. The initial value is 0 after power up.

Column 15

b7

b6

b5

b4

b3

b2

b1

b0

-

HORR

MSB

LSB

Column 16

b7

b6

b5

b4

b3

b2

b1

b0

-

-

-

RSPACE

MSB

LSB

Column 17

b7

b6

b5

b4

b3

b2

b1

b0

OSDEN

BSEN

SHADOW

FBEN

BLEND

WENCLR

RAMCLR

FBKGC

Column 18

B7

b6

b5

b4

b3

b2

b1

b0

TRIC

FSS

VMEN

SELVCL

HSP

VSP

VCO1

VCO0