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MTV030 Revision 1.0 10/15/1999

MTV030

MYSON

TECHNOLOGY

FSS - Font size selection.

= 1

⇒ 12x18 font size selected.

= 0

⇒ 12x16 font size selected.

VMEN - Auto sizing video measurement enable bit. All video measurements commence at the following VFLB

pulse after the VMEN bit is set, complete the measurement after one vertical frame.

SELVCL - Enable auto detection for horizontal and vertical syncs input edge distorition to avoid unstable

Vsync leading mismatch with Hsync signal while the bit is set to "1". The initial value is 0 after

power up.

HSP -

= 1

⇒ Accept positive polarity Hsync input.

= 0

⇒ Accept negative polarity Hsync input.

VSP -

= 1

⇒ Accept positive polarity Vsync input.

= 0

⇒ Accept negative polarity Vsync input.

VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and

horizontal resolution register (HORR).

= (0, 0)

⇒

6 MHz < Pixel rate < 28 MHz

= (0, 1)

⇒

28 MHz < Pixel rate < 56 MHz

= (1, 0)

⇒

56 MHz < Pixel rate < 112 MHz

= (1, 1)

⇒

112 MHz < Pixel rate < 150 MHz

where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12

The initial value is (0, 0) after power up.

Notes :

1. That is, if HORR is specified, then (VCO1, VCO0)

= (0, 0) if

6000/(HORR * 12) < HFLB Freq (KHz) < 28000/(HORR * 12)

= (0, 1) if

28000/(HORR * 12) < HFLB Freq (KHZ) < 56000/(HORR * 12)

= (1, 0) if

56000/(HORR * 12) < HFLB Freq (KHZ) < 112000/(HORR * 12)

= (1, 1) if 112000/(HORR * 12) < HFLB Freq (KHZ) < 150000/(HORR * 12)

2. It is necessary to wait for the PLL to become stable while (i) the HORR register is changed; (ii) the (VCO1, VCO0)

bits is changed; (iii) the horizontal signal (HFLB) is changed.

3. When PLL is unstable, don't write data in any address except Column 15,17,18 of Row 15. If data is written in any

other address, a malfunction may occur.

Fonts designed to be 12x18 display

FIGURE 7. 12x18 and 12x16 Fonts

Output display if FSS=0; first and last lines omitted