AD5451 datasheet(12/16 Pages) AD

12 / 16 page

–12–

REV. PrD

AD5450/AD5451/AD5452/AD5453

PRELIMINARY TECHNICAL DATA

CIRCUIT OPERATION

Unipolar Mode

Using a single op amp, these devices can easily be

configured to provide 2 quadrant multiplying operation or

a unipolar output voltage swing as shown in Figure 3.

When an output amplifier is connected in unipolar mode,

the output voltage is given by:

VOUT = -D/2

n x V

REF

Where D is the fractional representation of the digital

word loaded to the DAC, and n is the number of bits.

D = 0 to 255 (8-Bit AD5450)

= 0 to 1023 (10-Bit AD5451)

= 0 to 4095 (12-Bit AD5452)

= 0 to 16383 (14-Bit AD5453)

Note that the output voltage polarity is opposite to the

VREF polarity for dc reference voltages.

VOUT = 0 to -VREF

SCLK SDIN

VDD

GND

VREF

SYNC

IOUT1

RFB

VDD

VREF

uController

AGND

AD5450/1/2/3

NOTES:

1R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2C1 PHASE COMPENSATION (1pF - 5pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 3. Unipolar Operation

These DACs are designed to operate with either negative

or positive reference voltages. The VDD power pin is only

used by the internal digital logic to drive the DAC

switches’ ON and OFF states.

These DACs are also designed to accommodate ac refer-

ence input signals in the range of -10V to +10V.

With a fixed 10 V reference, the circuit shown above will

give an unipolar 0V to -10V output voltage swing. When

VIN is an ac signal, the circuit performs two-quadrant

multiplication.

The following table shows the relationship between digital

code and expected output voltage for unipolar operation.

(AD5450, 8-Bit device).

Table I. Unipolar Code Table

Digital Input

Analog Output (V)

1111 1111

-VREF (255/256)

1000 0000

-VREF (128/256) = -VREF/2

0000 0001

-VREF (1/256)

0000 0000

-VREF (0/256) = 0

Bipolar Operation

In some applications, it may be necessary to generate full

4-Quadrant multplying operation or a bipolar output

swing. This can be easily accomplished by using another

external amplifier and some external resistors as shown in

Figure 4. In this circuit, the second amplifier A2 provides

a gain of 2. Biasing the external amplifier with an offset

from the reference voltage results in full 4-quadrant

multiplying operation. The transfer function of this circuit

shows that both negative and positive output voltages are

created as the input data (D) is incremented from code

zero (VOUT = - VREF) to midscale (VOUT - 0V ) to full

scale (VOUT = + VREF).

VOUT = (VREF x D / 2

n-1 )

- VREF

Where D is the fractional representation of the digital

word loaded to the DAC and n is the resolution of the

DAC.

D = 0 to 255 (8-Bit AD5450)

= 0 to 1023 (10-Bit AD5451)

= 0 to 4095 (12-Bit AD5452)

= 0 to 16383 (14-Bit AD5453)

When VIN is an ac signal, the circuit performs four-

quadrant multiplication.

Table II. shows the relationship between digital code and

the expected output voltage for bipolar operation

(AD5450, 8-Bit device).

Figure 4. Bipolar Operation (4 Quadrant Multiplication)

VOUT

SCLK SDIN

VDD

VREF

± 10V

SYNC

GND

IOUT1

RFB

VDD

VREF

uController

NOTES:

1R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.

2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS

R3 AND R4.

3C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED

IF A1/A2 IS A HIGH SPEED AMPLIFIER.

10k

Ω

20k

Ω

AGND

= -VREFto+VREF

20k

Ω

AD5450/1/2/3

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