AD5451 datasheet(14/16 Pages) AD

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–14–

REV. PrD

AD5450/AD5451/AD5452/AD5453

PRELIMINARY TECHNICAL DATA

VOUT

VDD

GND

IOUT2

IOUT1

RFB

VDD

VREF

NOTES:

1ADDITIONAL PINS OMITTED FOR CLARITY

2C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

VIN

R1 = R2R3

R2 + R3

GAIN = R2 + R3

Figure 7. Increasing Gain of Current Output DAC

USED AS A DIVIDER OR PROGRAMMABLE GAIN

ELEMENT

Current Steering DACs are very flexible and lend

themselves to many different applications. If this type of

DAC is connected as the feedback element of an op-amp

and RFB is used as the input resistor as shown in Figure 8,

then the output voltage is inversely proportional to the

digital input fraction D. For D = 1-2

n the output voltage

VOUT = -VIN /D = -VIN /(1-2

-n)

VOUT

VDD

GND

VIN

IOUT1

RFB

VDD

VREF

NOTES:

1ADDITIONAL PINS OMITTED FOR CLARITY

Figure 8. Current Steering DAC used as a divider or

Programmable Gain Element

As D is reduced, the output voltage increases. For small

values of the digital fraction D, it is important to ensure

that the arnplifier does not saturate and also that the

required accuracy is met. For example, an eight bit DAC

driven with the binary code 10H (00010000), i.e., 16

decimal, in the circuit of Figure 8 should cause the output

voltage to be sixteen times VIN. However, if the DAC has

a linearity specification of +/- 0.5LSB then D

can in fact have the weight anywhere in the range 15.5/256

to 16.5/256 so that the possible output voltage will be in

the range 15.5VIN to 16.5VIN—an error of + 3% even

though the DAC itself has a maximum error of 0.2%.

DAC leakage current is also a potential error source in

divider circuits. The leakage current must be

counterbalanced by an opposite current supplied from the

op amp through the DAC. Since only a fraction D of the

current into the VREF terminal is routed to the IOUT1 ter-

minal, the output voltage has to change as follows:

Output Error Voltage Due to Dac Leakage

= (Leakage x R)/D

where R is the DAC resistance at the VREF terminal. For a

DAC leakage current of 10nA, R = 10 kilohm and a gain

(i.e., 1/D) of 16 the error voltage is 1.6mV.

REFERENCE SELECTION

When selecting a reference for use with the AD5426 series

of current output DACs, pay attention to the references

output voltage temperature coefficient specification. This

parameter not only affects the full scale error, but can also

affect the linearity (INL and DNL) performance. The

reference temperature coefficient should be consistent with

the system accuracy specifications. For example, an 8-bit

system required to hold its overall specification to within

1LSB over the temperature range 0-50

oC dictates that the

maximum system drift with temperature should be less than

78ppm/

oC. A 14-Bit system with the same temperature

range to overall specification within 2LSBs requires a

maximum drift of 10ppm/

oC. By choosing a

precision

reference with low output temperature coefficient this

error source can be minimized. Table IV. suggests some

of the suitable dc references available from Analog

Devices that are suitable for use with this range of current

output DACs.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is

an amplifier with low input bias currents and low input

offset voltage. The input offset voltage of an op amp is

multiplied by the variable gain (due to the code dependent

output resistance of the DAC) of the circuit. A change in

this noise gain between two adjacent digital fractions

produces a step change in the output voltage due to the

amplifier’s input offset voltage. This output voltage

change is superimposed upon the desired change in output

between the two codes and gives rise to a differential

linearity error, which if large enough could cause the

DAC to be non-monotonic.

The input bias curent of an op amp also generates an

offset at the voltage output as a result of the bias current

flowing in the feedback resistor RFB. Most op amps have

input bias currents low enough to prevent any significant

errors in 12-Bit applications, however for 14-Bit

applications some consideration should be given to

selecting an appropriate amplifier.

Common mode rejection of the op amp is important in

voltage switching circuits, since it produces a code

dependent error at the voltage output of the circuit. Most

op amps have adequate common mode rejection for use at

8-, 10- and 12-Bit resolution.

Provided the DAC switches are driven from true wideband

low impedance sources (VIN and AGND) they settle

quickly. Consequently, the slew rate and settling time of a

voltage switching DAC circuit is determined largely by

the output op amp. To obtain minimum settling time in

this configuration, it is important to minimize capacitance

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