SiC620, SiC620A

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Vishay Siliconix

S14-2385-Rev. E, 08-Dec-14

6

Document Number: 62922

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

This is the output applied to the power inductor and output

filter to deliver the output for the buck converter. The PHASE

is to be used exclusively as the return pin for the BOOT

capacitor. A 20 k

Ω resistor is connected between GH and

PHASE to provide a discharge path for the HS MOSFET in

circuit board should be such that the inductance separating

inductance effects between these two pins should not

exceed 0.5 V

the bias supply for the gate drivers. It is recommended to

separate these pins through a resistor. This creates a low

pass filtering effect to avoid coupling of high frequency gate

drive noise into the IC.

Bootstrap Circuit (BOOT)

The internal bootstrap diode and an external bootstrap

capacitor form a charge pump that supplies voltage to the

BOOT pin. An integrated bootstrap diode is incorporated so

that only an external capacitor is necessary to complete the

bootstrap circuit. Connect a boot strap capacitor with one

leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC620 and SiC620A have an internal adaptive logic to

avoid shoot through and optimize dead time. The shoot

through protection ensures that both high-side and low-side

MOSFETs are not turned ON at the same time. The adaptive

dead time control operates as follows. The HS and LS gate

voltages are monitored to prevent the one turning ON from

tuning ON until the other's gate voltage is sufficiently low

(< 1 V). Built in delays also ensure that one power MOS is

completely OFF, before the other can be turned ON. This

feature helps to adjust dead time as gate transitions change

with respect to output current and temperature. Change

with respect to output current and temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate

drive holding high-side and low-side MOSFET gates low

until the supply voltage rail has reached a point at which

the logic circuitry can be safely activated. The SiC620,

SiC620A also incorporates logic to clamp the gate drive

signals to zero when the UVLO falling edge triggers the

shutdown of the device. As an added precaution, a 20 k

Ω

resistor is connected between GH and PHASE to provide a

discharge path for the HS MOSFET.

FUNCTIONAL BLOCK DIAGRAM

Fig. 3 - SiC620 and SiC620A Functional Block Diagram

DISB#

20K

V

SWH

V

SWH

GL

+

-

GL

+

-

ZCD_EN#

Thermal monitor

& warning

UVLO

PWM logic

control &

state

machine

Anti-cross

conduction

control

logic

BOOT

THWn

GH

PWM

PHASE