SIC620 datasheet(12/20 Pages) VISHAY

12 / 20 page

SiC620, SiC620A

www.vishay.com

Vishay Siliconix

S14-2385-Rev. E, 08-Dec-14

Document Number: 62922

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

PCB LAYOUT RECOMMENDATIONS

Step 1: VIN/GND Planes and Decoupling

1. Layout VIN and PGND planes as shown above

2. Ceramic capacitors should be placed right between VIN

and PGND, and very close to the device for best

decoupling effect

3. Difference values / packages of ceramic capacitors

should be used to cover entire decoupling spectrum e.g.

1210, 0805, 0603 and 0402

4. Smaller capacitance value, closer to device VIN pin(s)

- better high frequency noise absorbing

Step 2: VSWH Plane

1. Connect output inductor to DrMOS with large plane to

lower the resistance

2. If

any

snubber

network

required,

place

the

components as shown above and the network can be

placed at bottom

Step 3: VCIN/VDRV Input Filter

1. The VCIN/VDRV input filter ceramic cap should be placed

very close to IC. It is recommended to connect two caps

separately.

2. CVCIN cap should be placed between pin 3 and pin 4

(CGND of driver IC) to achieve best noise filtering.

3. CVDRV cap should be placed between pin 28 (PGND of

driver IC) and pin 29 to provide maximum instantaneous

driver current for low-side MOSFET during switching

cycle

4. For connecting CVCIN analog ground, it is recommended

to use large plane to reduce parasitic inductance.

Step 4: BOOT Resistor and Capacitor Placement

1. These components need to be placed very close to IC,

right between PHASE (pin 7) and BOOT (pin 5).

2. To reduce parasitic inductance, chip size 0402 can be

used.

VIN

VSWH

PGND

VIN plane

PGND plane

PGND Plane

VSWH

PGND plane

GND

CVCIN

CVDRV

Cboot

Rboot

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