NSC800D datasheet(45/76 Pages) NSC

45 / 76 page

128 Bit Set Reset and Test (Continued)

BIT

B m1

Bit b in memory location m1 is tested via the Z flag

w m1b

S Undefined

Z Inverse of tested bit

H Set

PV Undefined

N Reset

C NA

76543210

BIT b (HL)

Timing

M cycles

T states

12 (4 4 4)

Addressing Mode

BitRegister Indirect

3210

BIT b (IXad) (for NXe0)

11NX 11101

BIT b (IYad) (for NXe1)

1011

110

Timing

M cycles

T states

20 (4 4 3 5 4)

Addressing Mode

BitIndexed

129 Rotate and Shift

RLC

Rotate register r left circular

TLC5171 – 57

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 7 of r

76543210

11001011

RLC r

(Note alternate for

A register below)

Timing

M cycles

T states

8 (4 4)

Addressing Mode

76543210

RLCA

Timing

M cycles

T states

Addressing Mode

Implied

(Note RLCA does not affect S Z or PV flags)

Rotate register r left through carry

TLC5171 – 58

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 7 of r

76543210

11001011

RL r

00010

(Note alternate for

A register below)

Timing

M cycles

T states

8 (4 4)

Addressing Mode

76543210

00010111

RLA

Timing

M cycles

T states

Addressing Mode

Implied

(Note RLA does not affect S Z or PV flags)

RRC

Rotate register r right circular

TLC5171 – 59

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 0 of r

NSC800D Datasheet(PDF) 45 Page - National Semiconductor (TI)

NSC800D Datasheet(HTML) 45 Page - National Semiconductor (TI)

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