NSC800D datasheet(46/76 Pages) NSC

46 / 76 page

129 Rotate and Shift (Continued)

76543210

11001011

RRC r

(Note alternate for

A register below)

Timing

M cycles

T states

8 (4 4)

Addressing Mode

76543210

RRCA

Timing

M cycles

T states

Addressing Mode

Implied

(Note RRCA does not affect S Z or PV flags)

Rotate register r right through carry

TLC5171 – 60

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 0 of r

76543210

11001001

RR r

00011

(Note alternate for

A register below)

Timing

M cycles

T states

8 (4 4)

Addressing Mode

76543210

00011111

RRA

Timing

M cycles

T states

Addressing Mode

Implied

(Note RRA does not affect S Z or PV flags)

SLA

Shift register r left arithmetric

TLC5171 – 61

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 7 of r

76543210

11001011

00100

Timing

M cycles

T states

8 (4 4)

Addressing Mode

SRA

Shift register r right arithmetic

TLC5171 – 62

S Set if result is negative

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 0 of r

76543210

11001011

00101

Timing

M cycles

T states

8 (4 4)

Addressing Mode

SRL

Shift register r right logical

TLC5171 – 63

S Reset

Z Set if result is zero

H Reset

PV Set if result parity is even

N Reset

C Set according to bit 0 of r

76543210

11001011

00111

Timing

M cycles

T states

8 (4 4)

Addressing Mode

NSC800D Datasheet(PDF) 46 Page - National Semiconductor (TI)

NSC800D Datasheet(HTML) 46 Page - National Semiconductor (TI)

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