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NSC800D Datasheet(PDF) 54 Page - National Semiconductor (TI) |
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NSC800D Datasheet(HTML) 54 Page - National Semiconductor (TI) |
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54 / 76 page  1212 InputOutput (Continued) INDR Data is input from the IO device at address (C) to memory location (HL) then the HL memory pointer is byte counter B are decremented The cycle is repeated until B e 0 (Note that B is tested for zero after it is decremented By loading B initially with zero 256 data transfers will take place) (HL) w (C) S Undefined HL w HL b 1 Z Set B w B b 1 H Undefined Repeat until B e 0 PV Undefined N Set C NA 76543210 11101101 10110010 Timing For B i 0 M cycles 5 T states 21 (4 5 3 4 5) For B e 0 M cycles 4 T states 16 (4 5 3 4) Addressing Mode ImpliedSource Register In- direct Destination Register Indirect (Note that after each data transfer cycle interrupts may be recognized and two refresh cycles are performed) OTDR Data is output from memory location (HL) to the IO device at port address (C) then the HL memory pointer and byte counter B are decremented The cycle is repeated until B e 0 (Note that B is tested for zero after it is decremented By loading B initially with zero 256 data transfers will take place) (C) w (HL) S Undefined HL w HL b 1 Z Set B w B b 1 H Undefined Repeat until B e 0 PV Undefined N Set C NA 76543210 11101101 10111011 Timing For B i 0 M cycles 5 T states 21 (4 5 3 4 5) For B e 0 M cycles 4 T states 16 (4 5 3 4) Addressing Mode ImpliedSource Register In- direct Destination Register Indirect (Note that after each data transfer cycle the NSC800 will accept interrupts and perform two refresh cycles) 1213 CPU Control NOP The CPU performs no operation No flags affected 76543210 00000000 Timing M cycles 1 T states 4 Addressing Mode NA HALT The CPU halts execution of the program Dummy op-code fetches are performed from the next memory location to keep the refresh circuits active until the CPU is interrupted or reset from the halted state No flags affected 76543210 01110110 Timing M cycles 1 T states 4 Addressing Mode NA DI Disable system level interrupts IFF1 w 0 No flags affected IFF2 w 0 76543210 11110011 Timing M cycles 1 T states 4 Addressing Mode NA EI The system level interrupts are enabled During execution of this instruction and the next one the maskable interrupts will be disabled IFF1 w 1 No flags affected IFF2 w 1 76543210 11111011 Timing M cycles 1 T states 4 Addressing Mode NA IM 0 The CPU is placed in interrupt mode 0 No flags affected 76543210 11101101 01000110 Timing M cycles 2 T states 8 (4 4) Addressing Mode NA 54 |
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