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NSC800D Datasheet(PDF) 55 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # NSC800D
Description  NSC800TM High-Performance Low-Power CMOS Microprocessor
PDF  76 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

NSC800D Datasheet(HTML) 55 Page - National Semiconductor (TI)

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1213 CPU Control (Continued)
IM
1
The CPU is placed in interrupt mode 1
No flags affected
76543210
11101101
01010110
Timing
M cycles
2
T states
8 (4 4)
Addressing Mode
NA
IM
2
The CPU is placed in interrupt mode 2
No flags affected
76543210
11101101
01011110
Timing
M cycles
2
T states
8 (4 4)
Addressing Mode
NA
1214 Program Control
JUMPS
JP
nn
Unconditional jump to program location nn
PC
w nn
No flags affected
76543210
11000011
n (low-order byte)
n (high-order byte)
Timing
M cycles
3
T states
10 (4 3 3)
Addressing Mode
Direct
JP
(ss)
Unconditional jump to program location pointed to by regis-
ter ss
PC
w ss
No flags affected
76543210
11101001
JP (HL)
Timing
M cycles
1
T states
4
Addressing Mode
Register Indirect
76
5
43210
JP (IX) (for NX e 0)
11NX 11101
JP (IY) (for NX e 1)
11
1
01001
Timing
M cycles
2
T states
8 (4 4)
Addressing Mode
Register Indirect
JP
cc nn
Conditionally jump to program location nn based on testable
flag states
If cc true
No flags affected
PC
w nn
otherwise continue
765
4
3210
11
cc
010
n (low-order byte)
n (high-order byte)
Timing
M cycles
3
T states
10 (4 3 3)
Addressing Mode
Direct
JR
d
Unconditional jump to program location calculated with re-
spect to the program counter and the displacement d
PC
w PC a d
No flags affected
76543210
00011000
d b 2
Timing
M cycles
3
T states
12 (4 3 5)
Addressing Mode
PC Relative
JR
kk d
Conditionally jump to program location calculated with re-
spect to the program counter and the displacement d
based on limited testable flag states
If kk true
No flags affected
PC
w PC a d
otherwise continue
76543210
001
kk
000
d b 2
Timing
if kk met
M cycles
3
(true)
T states
12 (4 3 5)
if kk not met
M cycles
2
(not true)
T states
7 (4 3)
Addressing Mode
PC Relative
55



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