NSC800D datasheet(20/76 Pages) NSC

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90 Timing and Control (Continued)

TLC5171 – 28

FIGURE 14 NSC800 Power-Save

TLC5171 – 22

S0 S1 during BREQ will indicate same machine cycle as during the cycle when BREQ was accepted

tZetime states during which bus and control signals are in high impedance mode

FIGURE 15 Bus Acknowledge Cycle

In the event BREQ is asserted (low) at the end of an instruc-

tion cycle and PS is active simultaneously the following oc-

curs

1 The NSC800 will go into BACK cycle

2 Upon completion of BACK cycle if PS is still active the

CPU will go into power-save mode

95 BUS ACCESS CONTROL

Figure 15 illustrates bus access control in the NSC800 The

external device controller produces an active BREQ signal

that requests the bus When the CPU responds with BACK

then the bus and related control strobes go to high imped-

ance (TRI-STATE) and the RFSH signal remains high It

should be noted that (1) BREQ is sampled at the last t state

of any M machine cycle only (2) The NSC800 will not ac-

knowledge any interruptrestart requests and will not pe-

form any dynamic RAM refresh functions until after BREQ

input signal is inactive high (3) BREQ signal has priority

over all interrupt request signals should BREQ and interrupt

request become active simultaneously Therefore interrupts

latched at the end of the instruction cycle will be serviced

after a simultaneously occurring BREQ NMI is latched dur-

ing an active BREQ

96 INTERRUPT CONTROL

The NSC800 has five interruptrestart inputs four are mask-

able (RSTA RSTB RSTC and INTR) and one is non-mask-

able (NMI) NMI has the highest priority of all interrupts the

user cannot disable NMI After recognizing an active input

on NMI the CPU stops before the next instruction pushes

the PC onto the stack and jumps to address X’0066 where

the user’s interrupt service routine is located (ie restart to

memory location X’0066) NMI is intended for interrupts re-

quiring immediate attention such as power-down control

panel etc

RSTA RSTB and RSTC are restart inputs which if enabled

execute a restart to memory location X’003C X’0034 and

X’002C respectively Note that the CPU response to the

NMI and RST (A B C) request input is basically identical

except for the restored memory location Unlike NMI how-

ever restart request inputs must be enabled

Figure 16 illustrates NMI and RST interrupt machine cycles

M1 cycle will be a dummy opcode fetch cycle followed by

M2 and M3 which are stack push operations The following

instruction then starts from the interrupts restart location

Note

RD does

not go low during this dummy opcode fetch A unique indica-

tion of INTA can be decoded using 2 ALEs and RD

NSC800D Datasheet(PDF) 20 Page - National Semiconductor (TI)

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