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Revision 3.0

Core Logic Module (Continued)

ROM Write Enable. When asserted, enables writes to ROM space, allowing Flash programming.

If strapped for ISA and this bit is set to 1, writes to the configured ROM space asserts ROMCS#, enabling the write cycle to

the Flash device on the ISA bus. Otherwise, ROMCS# is inhibited for writes.

If strapped for LPC and this bit is set to 1, the cycle runs on the LPC bus. Otherwise, the LPC bus cycle is inhibited for

writes.

Refer to F0BAR1+I/O Offset 10h[15] for further strapping/programming details.

Lower ROM Size. Selects lower ROM addressing size in which ROMCS# goes active.

0: Lower ROM access are 000F0000h-000FFFFFh (64 KB). (Default)

1: Lower ROM accesses are 000E0000h-000FFFFFh (128 KB).

ROMCS# goes active for the above ranges whether strapped for ISA or LPC. (Refer to F0BAR1+I/O Offset 10h[15] for fur-

ther strapping/programming details.)

The selected range can then be either positively or subtractively decoded through F0 Index 5Bh[5].

Index 53h

Alternate CPU Support Register (R/W)

Reset Value: 00h

7:6

Reserved. Must be set to 0.

Bidirectional SMI Enable.

0: Disable.

1: Enable.

This bit must be set to 0.

4:3

Reserved. Must be set to 0.

IRQ13 Function Selection. Selects function of the internal IRQ13/FERR# signal.

0: FERR#.

1: IRQ13.

This bit must be set to 1.

Generate SMI on A20M# Toggle.

0: Disable.

1: Enable.

This bit must be set to 1.

SMI status is reported at F1BAR0+I/O Offset 00h/02h[7].

Index 54h-59h

Reserved

Reset Value: 00h

Index 5Ah

Decode Control Register 1 (R/W)

Reset Value: 01h

Indicates PCI positive or negative decoding for various I/O ports on the ISA bus.

Note:

Positive decoding by the Core Logic module speeds up I/O cycle time. The I/O ports mentioned in the bit descriptions below, do

not exist in the Core Logic module. It is assumed that if positive decode is enabled for a port, the port exists on the ISA bus.

Secondary Floppy Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 372h-375h and

377h.

0: Subtractive.

1: Positive.

Primary Floppy Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3F2h-3F5h and

3F7h.

0: Subtractive.

1: Positive.

COM4 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 2E8h-2EFh.

0: Subtractive.

1: Positive.

COM3 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3E8h-3EFh.

0: Subtractive.

1: Positive.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

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