SC2200 datasheet(207/433 Pages) NSC

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Core Logic Module (Continued)

COM2 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 2F8h-2FFh.

0: Subtractive.

1: Positive.

COM1 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3F8h-3FFh.

0: Subtractive.

1: Positive.

Keyboard Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O Ports 060h and

064h (as well as 062h and 066h, if enabled - F4 Index 5Bh[7] = 1).

0: Subtractive.

1: Positive.

Note:

If F0BAR1+I/O Offset 10h bits 10 = 0 and 16 = 1, then this bit must be written 0.

Real-Time Clock Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O Ports 070h-073h.

0: Subtractive.

1: Positive.

Index 5Bh

Decode Control Register 2 (R/W)

Reset Value: 20h

Note:

Positive decoding by the Core Logic module speeds up the I/O cycle time. The Keyboard, LPT3, LPT2, and LPT1 I/O ports do

not exist in the Core Logic module. It is assumed that if positive decoding is enabled for any of these ports, the port exists on

the ISA bus.

Keyboard I/O Port 062h/066h Positive Decode. This alternate port to the keyboard controller is provided in support of

power management features.

0: Disable.

1: Enable.

Reserved. Must be set to 0.

BIOS ROM Positive Decode. Selects PCI positive or subtractive decoding for accesses to the configured ROM space.

0: Subtractive.

1: Positive.

ROM configuration is at F0 Index 52h[2:0].

Secondary IDE Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 170h-

177h and 376h-377h (excluding writes to 377h).

0: Subtractive. Subtractively decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are

then forwarded to ISA.

1: Positive. Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus.

Primary IDE Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 1F0h-

1F7h and 3F6h-3F7h (excluding writes to 3F7h).

0: Subtractive. Subtractively decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are

then forwarded to ISA.

1: Positive. Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus.

LPT3 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 278h-27Fh.

0: Subtractive.

1: Positive.

LPT2 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 378h-37Fh.

0: Subtractive.

1: Positive.

LPT1 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3BCh-3BFh

0: Subtractive.

1: Positive.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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