SC2200 datasheet(233/433 Pages) NSC

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Core Logic Module (Continued)

Offset 20h-23h

GPIO Signal Configuration Select Register (R/W)

Reset Value: 00000000h

31:6

Reserved. Must be set to 0.

5:0

Signal Select. Selects the GPIO signal to be configured in the Bank selected via bit 5 setting (i.e., Bank 0 or Bank 1). See

Table 3-2 on page 81 for GPIO ball muxing options. GPIOs without an associated ball number are not available externally.

Bank 0

000000 = GPIO0 (EBGA: H1 / TEPBGA: D11)

010000 = GPIO16 (EBGA: AL15 / TEPBGA: V31)

000001 = GPIO1 (EBGA: H2, AL12 / TEPBGA: D10, N30) 010001 = GPIO17 (EBGA: J4 / TEPBGA: A10)

000010 = GPIO2

010010 = GPIO18 (EBGA: A28 / TEPBGA: AG1)

000011 = GPIO3

010011 = GPIO19 (EBGA: H4 / TEPBGA: C9)

000100 = GPIO4

010100 = GPIO20 (EBGA: H3, AJ13 / TEPBGA: A9, N31)

000101 = GPIO5

010101 = GPIO21

000110 = GPIO6 (EBGA: AH3 / TEPBGA: D28)

010110 = GPIO22

000111 = GPIO7 (EBGA: AH4 / TEPBGA: C30)

010111 = GPIO23

001000 = GPIO8 (EBGA: AJ2 / TEPBGA: C31)

011000 = GPIO24

001001 = GPIO9 (EBGA: AG4 / TEPBGA: C28)

011001 = GPIO25

001010 = GPIO10 (EBGA: AJ1 / TEPBGA: B29)

011010 = GPIO26

001011 = GPIO11 (EBGA: H30 / TEPBGA: AJ8)

011011 = GPIO27

001100 = GPIO12 (EBGA: AJ12 / TEPBGA: N29)

011100 = GPIO28

001101 = GPIO13 (EBGA: AL11 / TEPBGA: M29)

011101 = GPIO29

001110 = GPIO14 (EBGA: F1 / TEPBGA: D9)

011110 = GPIO30

001111 = GPIO15 (EBGA: G3 / TEPBGA: A8)

011111 = GPIO31

Bank 1

100000 = GPIO32 (EBGA: AJ11 / TEPBGA: M28)

110000 = GPIO48

100001 = GPIO33 (EBGA: AL10 / TEPBGA: L31)

110001 = GPIO49

100010 = GPIO34 (EBGA: AK10 / TEPBGA: L30)

110010 = GPIO50

100011 = GPIO35 (EBGA: AJ10 / TEPBGA: L29)

110011 = GPIO51

100100 = GPIO36 (EBGA: AL9 / TEPBGA: L28)

110100 = GPIO52

100101 = GPIO37 (EBGA: AK9 / TEPBGA: K31)

110101 = GPIO53

100110 = GPIO38 (EBGA: AJ9 / TEPBGA: K28)

110110 = GPIO54

100111 = GPIO39 (EBGA: AL8 / TEPBGA: J31)

110111 = GPIO55

101000 = GPIO40 (EBGA: A21 / TEPBGA: Y3)

111000 = GPIO56

101001 = GPIO41 (EBGA: C19 / TEPBGA: W4)

111001 = GPIO57

101010 = GPIO42

111010 = GPIO58

101011 = GPIO43

111011 = GPIO59

101100 = GPIO44

111100 = GPIO60

101101 = GPIO45

111101 = GPIO61

101110 = GPIO46

111110 = GPIO62

101111 = GPIO47

111111 = GPIO63 (Note)

Note:

GPIO63 can be used to generate the PWRBTN# input signal. See PWRBTN# signal description in Section 2.4.15

"Power Management Interface Signals" on page 74.

Offset 24h-27h

GPIO Signal Configuration Access Register (R/W)

Reset Value: 00000044h

This register is used to indicate configuration for the GPIO signal that is selected in the GPIO Signal Configuration Select Register

(above).

Note:

PME debouncing, polarity, and edge/level configuration is only applicable on GPIO0-GPIO15 signals (Bank 0 = 00000 to

01111) and on GPIO32-GPIO47 signals (Bank 1 settings of 00000 to 01111). The remaining GPIOs (GPIO16-GPIO31 and

GPIO48-GPIO63) can not generate PMEs, therefore these bits have no function and read 0.

31:7

Reserved. Must be set to 0.

PME Debounce Enable. Enables/disables IRQ debounce (debounce period = 16 ms).

0: Disable.

1: Enable. (Default).

See the note in the description of this register for more information about the default value of this bit.

PME Polarity. Selects the polarity of the signal that issues a PME from the selected GPIO signal (falling/low or rising/high).

0: Falling edge or low level input. (Default)

1: Rising edge or high level input.

See the note in the description of this register for more information about the default value of this bit.

Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued)

Bit

Description

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