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Core Logic Module (Continued)

IRQ6 Source. Selects the interface source of the IRQ6 signal.

0: ISA - IRQ6. (Unavailable externally.)

1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)

IRQ5 Source. Selects the interface source of the IRQ5 signal.

0: ISA - IRQ5. (Unavailable externally.)

1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)

IRQ4 Source. Selects the interface source of the IRQ4 signal.

0: ISA - IRQ4. (Unavailable externally.)

1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)

IRQ3 Source. Selects the interface source of the IRQ3 signal.

0: ISA - IRQ3. (Unavailable externally.)

1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)

Reserved. Must be set to 0.

IRQ1 Source. Selects the interface source of the IRQ1 signal.

0: ISA - IRQ1. (Unavailable externally.)

1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)

IRQ0 Source. Selects the interface source of the IRQ0 signal.

0: ISA - IRQ0 (Internal signal - Connected to OUT0, System Timer, of the internal 8254 PIT.)

1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)

Offset 04h-07h

SERIRQ_LVL — Serial IRQ Level Control Register (R/W)

Reset Value: 00000000h

31:21

Reserved

INTD# Polarity. If LPC is selected as the interface source for INTD# (F0BAR1+I/O Offset 00h[20] = 1), this bit allows signal

polarity selection.

0: Active high.

1: Active low.

INTC# Polarity. If LPC is selected as the interface source for INTC# (F0BAR1+I/O Offset 00h[19] = 1), this bit allows signal

polarity selection.

0: Active high.

1: Active low.

INTB# Polarity. If LPC is selected as the interface source for INTB# (F0BAR1+I/O Offset 00h[18] = 1), this bit allows signal

polarity selection.

Active high.

Active low.

INTA# Polarity. If LPC is selected as the interface source for INTA# (F0BAR1+I/O Offset 00h[17] = 1), this bit allows signal

polarity selection.

0: Active high.

1: Active low.

Reserved. Must be set to 0.

IRQ15 Polarity. If LPC is selected as the interface source for IRQ15 (F0BAR1+I/O Offset 00h[15] = 1), this bit allows signal

polarity selection.

0: Active high.

1: Active low.

IRQ14 Polarity. If LPC is selected as the interface source for IRQ14 (F0BAR1+I/O Offset 00h[14] = 1), this bit allows signal

polarity selection.

0: Active high.

1: Active low.

IRQ13 Polarity. If LPC is selected as the interface source for IRQ13 (F0BAR1+I/O Offset 00h[13] = 1), this bit allows signal

polarity selection.

0: Active high.

1: Active low.

Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)

Bit

Description

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