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230

Revision 3.0

Core Logic Module (Continued)

Index F7h

Second Level PME/SMI Status Register 4 (RC)

Reset Value: 00h

The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].

Reading this register clears the status at both the second and top levels except for bit 7 which has a third level of status reporting at

F0BAR0+I/O 0Ch/1Ch.

A read-only “Mirror” version of this register exists at F0 Index 87h. If the value of the register must be read without clearing the SMI

source (and consequently deasserting SMI), F0 Index 87h can be read instead.

GPIO Event SMI Status (Read Only, Read does not Clear). Indicates whether or not an SMI was caused by a transition of

any of the GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0).

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0.

F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME and setting F1BAR1+I/O Offset 0Ch[0] =

0 enables the PME to generate an SMI. In addition, the selected GPIO must be enabled as an input (F0BAR0+I/O Offset

20h and 24h).

The next level (third level) of SMI status is at F0BAR0+I/O 0Ch/1Ch.

Thermal Override SMI Status. Indicates whether or not an SMI was caused by an assertion of the THRM#.

0: No.

1: Yes.

To enable SMI generation set F0 Index 83h[4] = 1.

5:4

Reserved. Read as 0.

SIO PWUREQ SMI Status. Indicates whether or not an SMI was caused by a power-up event from the SIO.

0: No.

1: Yes.

A power-up event is defined as any of the following events/activities:

—RI2#

—SDATA_IN2

— IRRX1 (CEIR)

To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0.

Codec SDATA_IN SMI Status. Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on

SDATA_IN.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 80h[5] = 1.

RTC Alarm (IRQ8#) SMI Status. Indicates whether or not an SMI was caused by an RTC interrupt.

0: No.

1: Yes.

This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs and F1BAR1+I/O Offset 0Ch[0] = 0.

ACPI Timer SMI Status. Indicates whether or not an SMI was caused by an ACPI Timer (F1BAR0+I/O Offset 1Ch or

F1BAR1+I/O Offset 1Ch) MSB toggle.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 83h[5] = 1.

Index F8h-FFh

Reserved

Reset Value: 00h

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

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