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Revision 3.0

Core Logic Module (Continued)

Index C4h-C7h

User Defined Device 2 Base Address Register (R/W)

Reset Value: 00000000h

31:0

User Defined Device 2 Base Address. This 32-bit register supports power management (Trap and Idle timer resources) for

a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the

device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).

The Core Logic module cannot snoop addresses on the Fast-PCI bus unless it actually claims the cycle. Therefore, Traps

and Idle timers cannot support power management of devices on the Fast-PCI bus.

Index C8h-CBh

User Defined Device 3 Base Address Register (R/W)

Reset Value: 00000000h

31:0

User Defined Device 3 Base Address. This 32-bit register supports power management (Trap and Idle timer resources) for

a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the

device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh).

The Core Logic module cannot snoop addresses on the Fast-PCI bus unless the it actually claims the cycle. Therefore,

Traps and Idle timers cannot support power management of devices on the Fast-PCI bus.

Index CCh

User Defined Device 1 Control Register (R/W)

Reset Value: 00h

Memory or I/O Mapped. Determines how User Defined Device 1 is mapped.

0: I/O.

1: Memory.

6:0

Mask.

If bit 7 = 0 (I/O):

Bit 6

0: Disable write cycle tracking

1: Enable write cycle tracking

Bit 5

0: Disable read cycle tracking

1: Enable read cycle tracking

Bits [4:0] Mask for address bits A[4:0]

If bit 7 = 1 (Memory):

Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.

Note:

A "1" in a mask bit means that the address bit is ignored for comparison.

Index CDh

User Defined Device 2 Control Register (R/W)

Reset Value: 00h

Memory or I/O Mapped. determines how User Defined Device 2 is mapped.

0: I/O

1: Memory

6:0

Mask.

If bit 7 = 0 (I/O):

Bit 6

0: Disable write cycle tracking

1: Enable write cycle tracking

Bit 5

0: Disable read cycle tracking

1: Enable read cycle tracking

Bits [4:0] Mask for address bits A[4:0]

If bit 7 = 1 (Memory):

Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.

Note:

A "1" in a mask bit means that the address bit is ignored for comparison.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

SC2200 Datasheet(PDF) 226 Page - National Semiconductor (TI)

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