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SC2200 Datasheet(PDF) 252 Page - National Semiconductor (TI) |
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SC2200 Datasheet(HTML) 252 Page - National Semiconductor (TI) |
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252 / 433 page  www.national.com 252 Revision 3.0 Core Logic Module (Continued) 5 EXT_SMI5 SMI Enable. When this bit is asserted, allow EXT_SMI5 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 21 (RC) and 13 (RO). 4 EXT_SMI4 SMI Enable. When this bit is asserted, allows EXT_SMI4 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 20 (RC) and 12 (RO). 3 EXT_SMI3 SMI Enable. When this bit is asserted, allow EXT_SMI3 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 19 (RC) and 11 (RO). 2 EXT_SMI2 SMI Enable. When this bit is asserted, allow EXT_SMI2 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 18 (RC) and 10 (RO). 1 EXT_SMI1 SMI Enable. When this bit is asserted, allow EXT_SMI1 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 17 (RC) and 9 (RO). 0 EXT_SMI0 SMI Enable. When this bit is asserted, allow EXT_SMI0 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 16 (RC) and 8 (RO). Offset 28h-4Fh Not Used Reset Value: 00h Offset 50h-FFh The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) can also be accessed at F0 Index 50h-FFh. The pre- ferred method is to program these registers through the F0 register space. Refer to Table 5-29 "F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support" on page 199 for more information about these registers. Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit Description |
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