SC2200 datasheet(251/433 Pages) NSC

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Core Logic Module (Continued)

EXT_SMI0 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.

0: No.

1: Yes.

To enable SMI generation, set bit 0 to 1.

EXT_SMI7 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI7.

0: No.

1: Yes.

To enable SMI generation, set bit 7 to 1.

EXT_SMI6 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6.

0: No.

1: Yes.

To enable SMI generation, set bit 6 to 1.

EXT_SMI5 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.

0: No.

1: Yes.

To enable SMI generation, set bit 5 to 1.

EXT_SMI4 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.

0: No.

1: Yes.

To enable SMI generation, set bit 4 to 1.

EXT_SMI3 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.

0: No.

1: Yes.

To enable SMI generation, set bit 3 to 1.

EXT_SMI2 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2.

0: No.

1: Yes.

To enable SMI generation, set bit 2 to 1.

EXT_SMI1 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1.

0: No.

1: Yes.

To enable SMI generation, set bit 1 to 1.

EXT_SMI0 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.

0: No.

1: Yes.

To enable SMI generation, set bit 0 to 1.

EXT_SMI7 SMI Enable. When this bit is asserted, allow EXT_SMI7 to generate an SMI on negative-edge events.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+00h/02h[10].

Second level SMI status is reported at bits 23 (RC) and 15 (RO).

EXT_SMI6 SMI Enable. When this bit is asserted, allow EXT_SMI6 to generate an SMI on negative-edge events.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+00h/02h[10].

Second level SMI status is reported at bits 22 (RC) and 14 (RO).

Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)

Bit

Description

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