SC2200 datasheet(249/433 Pages) NSC

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Core Logic Module (Continued)

Offset 20h-21h

Second Level ACPI PME/SMI

Reset Value: 0000h

Status Mirror Register (RO)

The bits in this register contain second level SMI status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[2].

Reading this register does not clear the SMI. For more information, see F1BAR0+I/O Offset 22h.

15:6

Reserved. Always reads 0.

ACPI BIOS SMI Status. Indicates whether or not an SMI was caused by ACPI software raising an event to BIOS software.

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 0Ch[2] to 1, and F1BAR1+I/O Offset 0Fh[0] to 1.

PLVL3 SMI Status. Indicates whether or not an SMI was caused by a read of the ACPI PLVL3 register (F1BAR1+I/O Offset

05h).

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 18h[11] to 1 (default).

Reserved.

SLP_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI SLP_EN bit (F1BAR1+I/O

Offset 0Ch[13]).

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 18h[9] to 1 (default).

THT_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI THT_EN bit (F1BAR1+I/O

Offset 00h[4]).

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 18h[8] to 1 (default).

SMI_CMD SMI Status. Indicates whether or not an SMI was caused by a write to the ACPI SMI_CMD register

(F1BAR1+I/O Offset 06h).

0: No.

1: Yes.

A write to the ACPI SMI_CMD register always generates an SMI.

Offset 22h-23h

Second Level ACPI PME/SMI Status Register (RC)

Reset Value: 0000h

The bits in this register contain second level of SMI status reporting. Top level is reported in F1BAR0+I/O Offset 00h/02h[2].

Reading this register clears the status at both the second and top levels.

A read-only “Mirror” version of this register exists at F1BAR0+I/O Offset 20h. If the value of the register must be read without clearing the

SMI source (and consequently deasserting SMI), F1BAR0+I/O Offset 20h can be read instead.

15:6

Reserved. Always reads 0.

ACPI BIOS SMI Status. Indicates whether or not an SMI was caused by ACPI software raising an event to BIOS software.

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 0Ch[2] to 1, and F1BAR1+I/O Offset 0Fh[0] to 1.

PLVL3 SMI Status. Indicates whether or not an SMI was caused by a read of the ACPI PLVL3 register (F1BAR1+I/O Offset

05h).

0: No.

1: Yes.

To enable SMI generation, set F1BAR1+I/O Offset 18h[11] to 1 (default).

Reserved.

Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)

Bit

Description

SC2200 Datasheet(PDF) 249 Page - National Semiconductor (TI)

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