SC2200 datasheet(247/433 Pages) NSC

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Core Logic Module (Continued)

Offset 04h-05h

Second Level General Traps & Timers

Reset Value: 0000h

PME/SMI Status Mirror Register (RO)

The bits in this register contain second level status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[9].

Reading this register does not clear the SMI. For more information, see F1BAR0+I/O Offset 06h.

15:6

Reserved.

PCI/ISA Function Trap. Indicates whether or not an SMI was caused by a trapped PCI/ISA configuration cycle.

0: No.

1: Yes.

To enable SMI generation for:

— Trapped access to ISA Legacy I/O register space set F0 Index 41h[0] = 1.

— Trapped access to F1 register space set F0 Index 41h[1] = 1.

— Trapped access to F2 register space set F0 Index 41h[2] = 1.

— Trapped access to F3 register space set F0 Index 41h[3] = 1.

— Trapped access to F4 register space set F0 Index 41h[4] = 1.

— Trapped access to F5 register space set F0 Index 41h[5] = 1.

SMI Source is Trapped Access to User Defined Device 3. Indicates whether or not an SMI was caused by a trapped I/O

or memory access to the User Defined Device 3 (F0 Index C8h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 82h[6] = 1.

SMI Source is Trapped Access to User Defined Device 2. Indicates whether or not an SMI was caused by a trapped I/O

or memory access to the User Defined Device 2 (F0 Index C4h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 82h[5] = 1.

SMI Source is Trapped Access to User Defined Device 1. Indicates whether or not an SMI was caused by a trapped I/O

or memory access to the User Defined Device 1 (F0 Index C0h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 82h[4] = 1.

SMI Source is Expired General Purpose Timer 2. Indicates whether or not an SMI was caused by the expiration of Gen-

eral Purpose Timer 2 (F0 Index 8Ah).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 83h[1] = 1.

SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI was caused by the expiration of Gen-

eral Purpose Timer 1 (F0 Index 88h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 83h[0] = 1.

Offset 06h-07h

Second Level General Traps & Timers Status Register (RC)

Reset Value: 0000h

The bits in this register contain second level of status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[9]. Reading

this register clears the status at both the second and top levels.

A read-only “Mirror” version of this register exists at F1BAR0+I/O Offset 04h. If the value of this register must be read without clearing

the SMI source (and consequently deasserting SMI), F1BAR0+I/O Offset 04h can be read instead.

15:6

Reserved.

Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)

Bit

Description

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