SC2200 datasheet(258/433 Pages) NSC

258 / 433 page

www.national.com

258

Revision 3.0

Core Logic Module (Continued)

GPIO_STS. Indicates if PME was caused by activity on any of the GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0).

0: No.

1: Yes.

Write 1 to clear.

For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[3] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the

general description of this register above).

F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME. In addition, the selected GPIO must be

enabled as an input (F0BAR0+I/O Offset 20h and 24h).

2:1

Reserved. Reads as 0.

PWR_U_REQ_STS. Indicates if PME was caused by a power-up request event from the SuperI/O module.

0: No.

1: Yes.

Write 1 to clear.

For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[0] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the

general description of this register above.)

Offset 12h-13h

GPE0_EN — General Purpose Event 0 Enable Register (R/W)

Reset Value: 0000h

In order for the ACPI events described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0] = 1).

The SCIs enabled in this register are globally enabled by setting F1BAR1+I/O Offset 0Ch[0] to 1. The status of the SCIs is reported in

F1BAR1+I/O Offset 10h.

15:12

Reserved.

GPWIO2_EN. Allow GPWIO2 to generate an SCI.

0: Disable.

1: Enable.

A fixed high-to-low or low-to-high transition (debounce period) of 31 µs exists in order for GPWIO2 to be recognized.

The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[6] to force an SMI.

GPWIO1_EN. Allow GPWIO1 to generate an SCI.

0: Disable.

1: Enable.

See F1BAR1+I/O Offset 07h[3] for debounce information.

The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[5] to force an SMI.

GPWIO0_EN. Allow GPWIO0 to generate an SCI.

0: Disable.

1: Enable.

See F1BAR1+I/O Offset 07h[3] for debounce information.

The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[4] to force an SMI.

Reserved. Must be set to 0

USB_EN. Allow USB events to generate a SCI.

0: Disable.

1: Enable

THRM_EN. Allow THRM# to generate an SCI.

0: Disable.

1: Enable

SMI_EN. Allow SMI events to generate an SCI.

0: Disable.

1: Enable

Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)

Bit

Description

SC2200 Datasheet(PDF) 258 Page - National Semiconductor (TI)

SC2200 Datasheet(HTML) 258 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL