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Core Logic Module (Continued)

Read: PortResetStatus.

0: Port reset signal is not active.

1: Port reset signal is active.

Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect.

Read: PortOverCurrentIndicator. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only

valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.

0: No over-current condition.

1: Over-current condition.

Write: ClearPortSuspend. Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect.

Read: PortSuspendStatus.

0: Port is not suspended.

1: Port is selectively suspended.

Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect.

Read: PortEnableStatus.

0: Port disabled.

1: Port enabled.

Write: SetPortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.

Read: CurrentConnectStatus.

0: No device connected.

1: Device connected.

If DeviceRemoveable is set (not removable) this bit is always 1.

Write: ClearPortEnable. Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.

Note:

This register is reset by the UsbReset state.

Offset 5Ch-5Fh

HcRhPortStatus[3] Register (R/W)

Reset Value = 00000000h

31:21

Reserved. Read/Write 0s.

PortResetStatusChange. This bit indicates that the port reset signal has completed.

0: Port reset is not complete.

1: Port reset is complete.

PortOverCurrentIndicatorChange. This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing

a 0 has no effect.

PortSuspendStatusChange. This bit indicates the completion of the selective resume sequence for the port.

0: Port is not resumed.

1: Port resume is complete.

PortEnableStatusChange. This bit indicates that the port has been disabled due to a hardware event (cleared PortEna-

bleStatus).

0: Port has not been disabled.

1: PortEnableStatus has been cleared.

ConnectStatusChange. This bit indicates a connect or disconnect event has been detected. Writing a 1 clears this bit.

Writing a 0 has no effect.

0: No connect/disconnect event.

1: Hardware detection of connect/disconnect event.

If DeviceRemoveable is set, this bit resets to 1.

15:10

Reserved. Read/Write 0s.

Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)

Bit

Description

SC2200 Datasheet(PDF) 298 Page - National Semiconductor (TI)

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