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SC2200 Datasheet(PDF) 385 Page - National Semiconductor (TI) |
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SC2200 Datasheet(HTML) 385 Page - National Semiconductor (TI) |
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385 / 433 page ![]() Revision 3.0 385 www.national.com Electrical Specifications (Continued) 8.3.6 Sub-ISA Interface All output timing is guaranteed for 50 pF load, unless otherwise specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. Table 8-21. Sub-ISA Timing Parameters Symbol Parameter Bus Width (Bits) Type Min (ns) Max (ns) Figure Comments tRD1 MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 16 M 225 8-19 Standard tRD2 MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 16 M 105 8-19 Zero wait state tRD3 IOR#/RD#/TRDE# Read active pulse widthFE toRE 16 I/O 160 8-19 Standard tRD4 IOR#/MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 8 M, I/O 520 8-19 Standard tRD5 IOR#/MEMR#/DOCR#/RD#/TRDE# Read active pulse width FE to RE 8 M, I/O 160 8-19 Zero wait state tRCU1 MEMR#/DOCR#/RD#/TRDE# inactive pulse width 16 M 103 8-19 tRCU2 MEMR#/DOCR#/RD#/TRDE# inactive pulse width 8 M 163 8-19 tRCU3 IOR#/RD#/TRDE# inactive pulse width 8, 16 I/O 163 8-19 tWR1 MEMW#/WR# Write active pulse widthFE toRE 16 M 225 8-20 Standard tWR2 MEMW#/DOCW#/WR# Write active pulse width FE to RE 16 M 105 8-20 Zero wait state tWR3 IOW#/WR# Write active pulse width FE to RE 16 I/O 160 8-20 Standard tWR4 IOW#/MEMW#/DOCW#/WR# Write active pulse width FE to RE 8 M, I/O 520 8-20 Standard tWR5 IOW#/MEMW#/DOCW#/WR# Write active pulse width FE to RE 8 M, I/O 160 8-20 Zero wait state tWCU1 MEMW#/WR#/DOCW# inactive pulse width 16 M 103 8-20 tWCU2 MEMW#/WR#/DOCW# inactive pulse width 8 M 163 8-20 tWCU3 IOW#/WR# inactive pulse width 8, 16 I/O 163 8-20 tRDYH IOR#/MEMR#/RD#/DOCR#/IOW#/ MEMW#/WR#/DOCW# Hold after IOCHRDY RE 8, 16 M, I/O 120 8-19 8-20 tRDYA1 IOCHRDY valid after IOR#/MEMR#/ RD#/DOCR#/IOW#/MEMW#/WR#/ DOCW# FE 16 M, I/O 78 8-19 8-20 |
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