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Electrical Specifications (Continued)

Table 8-26. Multiword DMA Data Transfer Timing Parameters

Symbol

Parameter

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

Cycle time1 (min)

t0 is the minimum total cycle time, tD is the minimum command active time, and tKR or tKW is the minimum command

recovery time or command inactive time. The actual cycle time equals the sum of the command active time and the

command inactive time. The three timing requirements of t0,tD and tKR/KW, are met. The minimum total cycle time re-

quirement t0 is greater than the sum of tD and tKR/KW. (This means that a host implementation can lengthen tD and/or

tKR/KW to ensure that t0 is equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)

480

150

120

IDE_IOR[0:1]#/IDE_IOW[0:1]# (min)

215

IDE_IOR[0:1]# data access (max)

150

IDE_IOR[0:1]# data hold (min)

IDE_IOW[0:1]#/IDE_IOW[0:1]# data setup (min)

100

IDE_IOW[0:1]# data hold (min)

IDE_DACK[0:1]# to IDE_IOR[0:1]#/IDE_IOW[0:1]# setup (min)

IDE_IOR[0:1]#/IDE_IOW[0:1]# to IDE_DACK[0:1]# hold (min)

tKR

IDE_IOR[0:1]# negated pulse width (min)

tKW

IDE_IOW[0:1]# negated pulse width (min)

215

tLR

IDE_IOR[0:1]# to IDE_DREQ[0:1] delay (max)

120

tLW

IDE_IOW[0:1]# to IDE_DREQ0,1 delay (max)

IDE_CS[0:1]# valid to IDE_IOR[0:1]#/IDE_IOW[0:1]# (min)

IDE_CS[0:1]# hold

IDE_DACK[0:1]# to TRI-STATE

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