SC2200 datasheet(109/433 Pages) NSC

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SuperI/O Module (Continued)

4.4.2.2

LDN 01h - System Wakeup Control

Table 4-8 lists registers that are relevant to the configura-

tion of System Wakeup Control (SWC). These registers are

described earlier in Table 4-3 "Standard Configuration Reg-

isters" on page 104.

Table 4-8. Relevant SWC Registers

Index

Type

Configuration Register or Action

Reset

Value

30h

R/W

Activate. When bit 0 is cleared, the registers of this logical device are not accessible.1

00h

60h

R/W

Base Address MSB register.

00h

61h

R/W

Base Address LSB register. Bits [3:0] (for A[3:0]) are RO, 0000b.

00h

70h

R/W

Interrupt Number. (For routing the internal PWUREQ signal.)

00h

71h

R/W

Interrupt Type. Bit 1 is R/W. Other bits are RO.

03h

74h

Report no DMA assignment.

04h

75h

Report no DMA assignment.

04h

The logical device registers are maintained, and all wakeup detection mechanisms are functional.

SC2200 Datasheet(PDF) 109 Page - National Semiconductor (TI)

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