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SC2200 Datasheet(PDF) 189 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # SC2200
Description  Thin Client On a Chip
PDF  433 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SC2200 Datasheet(HTML) 189 Page - National Semiconductor (TI)

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Revision 3.0
189
www.national.com
Core Logic Module (Continued)
Table 5-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
F1 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-32)
00h-01h
16
RO
Vendor Identification Register
100Bh
Page 243
02h-03h
16
RO
Device Identification Register
0501h
Page 243
04h-05h
16
R/W
PCI Command Register
0000h
Page 243
06h-07h
16
RO
PCI Status Register
0280h
Page 243
08h
8
RO
Device Revision ID Register
00h
Page 243
09h-0Bh
24
RO
PCI Class Code Register
068000h
Page 243
0Ch
8
RO
PCI Cache Line Size Register
00h
Page 243
0Dh
8
RO
PCI Latency Timer Register
00h
Page 243
0Eh
8
RO
PCI Header Type Register
00h
Page 243
0Fh
8
RO
PCI BIST Register
00h
Page 243
10h-13h
32
R/W
Base Address Register 0 (F1BAR0) — Sets the base address for
the I/O mapped SMI Status Registers (summarized in Table 5-18).
00000001h
Page 243
14h-2Bh
---
---
Reserved
00h
Page 243
2Ch-2Dh
16
RO
Subsystem Vendor ID
100Bh
Page 243
2Eh-2Fh
16
RO
Subsystem ID
0501h
Page 243
30h-3Fh
---
---
Reserved
00h
Page 243
40h-43h
32
R/W
Base Address Register 1 (F1BAR1) — Sets the base address for
the I/O mapped ACPI Support Registers (summarized in Table 5-
19)
00000001h
Page 243
44h-FFh
---
---
Reserved
00h
Page 243
Table 5-18. F1BAR0: SMI Status Registers Summary
F1BAR0+
I/O Offset
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-33)
00h-01h
16
RO
Top Level PME/SMI Status Mirror Register
0000h
Page 244
02h-03h
16
RO/RC
Top Level PME/SMI Status Register
0000h
Page 245
04h-05h
16
RO
Second Level General Traps & Timers PME/SMI Status Mirror
Register
0000h
Page 247
06h-07h
16
RC
Second Level General Traps & Timers PME/SMI Status Register
0000h
Page 247
08h-09h
16
Read to
Enable
SMI Speedup Disable Register
0000h
Page 248
0Ah-1Bh
---
---
Reserved
00h
Page 248
1Ch-1Fh
32
RO
ACPI Timer Register
xxxxxxxxh
Page 248
20h-21h
16
RO
Second Level ACPI PME/SMI Status Mirror Register
0000h
Page 249
22h-23h
16
RC
Second Level ACPI PME/SMI Status Register
0000h
Page 249
24h-27h
32
R/W
External SMI Register
00000000h
Page 250
28h-4Fh
---
---
Not Used
00h
Page 252
50h-FFh
---
---
The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) are also accessible at F0
Index 50h-FFh. The preferred method is to program these registers through the F0 register space.



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