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TP3410 Datasheet(PDF) 27 Page - National Semiconductor (TI) |
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TP3410 Datasheet(HTML) 27 Page - National Semiconductor (TI) |
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27 / 32 page  Timing Characteristics Symbol Parameter Conditions Min Typ Max Units FMCK Master Clock Frequency Including Temperature Aging Etc 1536 MHz Master Clock Tolerance b 100 a 100 ppm MCLKXTAL Input Clock Jitter External Clock Source 50 ns pk-pk tMH Clock Pulse Width VIH e VCC b 05V 20 ns tML Hi Low for MCLK VIL e 05V tMR Rise and Fall Time Used as a Logic Input 10 ns tMF of MCLK DIGITAL INTERFACE ( Figures 11 12 and 13 ) FBCLK Frequency of BCLK Formats 1 2 and 3 256 4096 kHz GCI and Format 4 512 6144 kHz tWBH Period of BCLK High Measured from VIH to VIH (Input) 25 ns tWBL Period of BCLK Low Measured from VIL to VIL (Input) 25 ns tRB Rise Time of BCLK Measured from VIL to VIH (Input) 15 ns tFB Fall Time of BCLK Measured from VIH to VIL (Input) 15 ns tSFB Setup Time FS High DSI or GCI Slave Only 50 ns to BCLK Low tHBF Hold Time BCLK Low DSI or GCI Slave Only 25 ns to FS High or Low tDBF Delay Time BCLK High DSI or GCI Master Only 50 ns to FSa and FSb Transitions tDBD Delay Time BCLK High All Modes 80 ns to Data Valid Load e 150 pF Plus 2 LSTTL Loads tDBZ Delay Time BCLK High All Modes 55 ns to Br Dr Disabled tDBT Delay Time BCLK High to Load e 100 pF Plus 2 LSTTL Loads TSr Low if FS High or 55 ns FS High to TSr Low if BCLK High tZBT TRI-STATE Time BCLK 55 ns Low to TSr High tDFD Delay Time FS Load e 150 pF Plus 2 LSTTL Loads High to Data Valid Applies if FS Rises Later than 80 ns BCLK Rising Edge in Non-Delayed Data Mode Only tSDB Setup Time Data All Modes 0ns Valid to BCLK Low tHBD Hold Time BCLK All Modes 25 ns Low to Data Invalid 27 |
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