TP3410 datasheet(19/32 Pages) NSC

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Functional Description (Continued)

RFS Remote Febe Select

RFS e1 (default state)

The state of the outgoing bit is computed based on the state

of the TFB (bit 1) in TXM56 register The TFB blt is set e 0

by the software to allow a febe blt from an adjacent DSL to

be forwarded to the next section in the next superframe

This bit is self resetting (to 1) in Rev 3x devices This is a

change from the Rev 2x devices If RFS e 0 then the

outgoing febe does not depend on the state of the TFB blt

in TXM56 register

LFS Local Febe Select

LFS e1 (default state)

The state of the outgoing febe bit is computed using the

incoming nebe blt If LFS e 0 the outgoing febe is not

dependent on the incoming nebe

Example of use

A flexible control of the outgoing febe bit is provided to sup-

port the Segmented and Path Performance Monitoring rec-

ommendations in Bellcore TR 397

For Rev 28 type operation set RFS e 1 LFS e 1 and

TFB0 e 1 This setting will cause the transmit febe to be

computed as OR of the incoming nebe blt and the state of

the TFB bit in TXM56 (representing the adjacent section

febe to be forwarded)

97 Configuration Registers TXB1 TXB2 RXB1

RXB2 B Channel TSA

These registers are effective only when Format 3 is select-

TXB1 assigns the Transmit time slot for the B1 channel

TXB2 assigns the Transmit time slot for the B2 channel

RXB1 assigns the Receive time slot for the B1 channel

RXB2 assigns the Receive time slot for the B2 channel

Byte 2

543210

TS5

TS4

TS3

TS2

TS1

TS0

At Power-On Reset this register is initialized to X 00

Byte 2

543210

TS5

TS4

TS3

TS2

TS1

TS0

At Power-On Reset this register is initialized to X 01

Byte 2

543210

EB1

TS5

TS4

TS3

TS2

TS1

TS0

At Power-On Reset this register is initialized to X 00

Byte 2

543210

EB2

TS5

TS4

TS3

TS2

TS1

TS0

At Power-On Reset this register is initialized to X 01

B Channels Time-Slot Assignment TS5 – TS0

The TS5 – TS0 bits define the binary number of the time-slot

when the B channel selected is shifted to or from the Bx and

Br pins time-slots are numbered from 0 to 63 New time-slot

assignments become effective only at the beginning of a

frame

B1 and D Channel Enables EB1 ED

EB1 e 0 to disable the B1 channel B1 is high-impedance

at Br

EB1 e 1 to enable the B1 channel (must also set DDe0in

CR2)

ED e 0 to disable the D channel D is high-impedance at

Br or Dr

ED e 1 to enable the D channel (must also set DDe0in

CR2)

B2 Channel Enable EB2

EB2 e 0 to disable the B2 channel B2 is high-impedance

at Br

EB2 e 1 to enable the B2 channel (must also set DDe0in

CR2)

98 Configuration Register TXD

Transmit D Channel TSA

This register is effective only when Format 3 is selected D

channel TSA may be used when the D channel is accessed

either via the BxBr or DxDr pins but the D channel port

must be clocked with BCLK (DMO e 0 in CR2)

Byte 2

765432

DX5

DX4

DX3

DX2

DX1

DX0

SX1

SX0

At Power-On Reset this register is initialized to X 08

Transmit D Channel Time-Slot Assignment Select

DX5 – DX0 SX1 – SX0

DX5 – DX0 bits define the binary number of the 8-bit wide

time-slot where time-slots are numbered from 0 to 63 With-

in this selected time-slot the SX1 and SX0 bits define the 2-

bit wide sub-slot for the 2 D channel bits Sub-slots are num-

bered 0 to 3 as shown in

Figures 5 11 and 12 and the

following table New time-slot and sub-slot assignments be-

come effective only at the beginning of a frame

Sub-Slot

Bit Positions

SX1

SX0

within Time-Slot

1 2

3 4

5 6

7 8

99 Configuration Register RXD

Receive D Channel TSA

This register is effective only when Format 3 is selected D

channel TSA may be used when the D channel is accessed

either via the BxBr or DxDr pins but the D channel port

must be selected in the burst mode (DMO e 0 in CR2)

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