TP3410 datasheet(20/32 Pages) NSC

20 / 32 page

Functional Description (Continued)

Byte 2

765432

DR5

DR4

DR3

DR2

DR1

DR0

SR1

SR0

At Power-On Reset this register is initialized to X 08

Receive D Channel Time-Slot Assignment Select

DR5 – DR0 SR1 – SR0

DR5 – DR0 bits define the binary number of the 8-bit wide

time-slot where the time-slots are numbered from 0 to 63

Within this selected time-slot the SR1 and SR0 bits define

the binary number of the 2 D channel bits Sub-slots are

numbered 0 to 3 as shown in

Figure 12 and the following

table New time-slot and sub-slot assignments become ef-

fective only at the beginning of a frame

Sub-Slot

Bit Positions

SR1

SR0

within Time-Slot

1 2

3 4

5 6

7 8

910 Configuration Register OPR

Overhead Bit Processing

This register controls the enablingdisabling of conditions

which are sent to the Interrupt Stack (see 101) as a result

of new data in the RXM4 and RXM56 Overhead Bits Regis-

ters and the number of consecutive times a new bit or mes-

sage is received before being validated Flexibility is there-

fore provided to use hardware external firmware routines or

a combination of both for validation

Byte 2

CIE

EIE

FIE

OB1

OB0

OC1

OC0

At Power-On Reset this register is initialized to X 00

Near-End CRC Interrupt Enable CIE

CIE

No Interrupt if near-end crc error (Block Error

Counters still count)

RXM56 Status Register Interrupt is generated with

NEB e 0 each superframe in which the locally-

generated crc result does not match the crc in the

received superframe

Block Error Counter Interrupt Enable EIE

EIE

No Interrupt or Monitor channel message from

Block Error Counters

Block Error Counter Interrupts enabled

febe Bit Interrupt Enable FIE

FIE

No Interrupt if febee0 received (BEC1 still counts)

RXM56 Status Register Interrupt is generated with

RFB e 0 each superframe in which febee0is

received

Receive Overhead Bits Interrupt Enable 0B1 0B0

These bits determine how many consecutive superframes

must be received with the same new data in any of the

overhead bit positions M41 – M48 M51 M52 andor M61

before an Interrupt(s) is generated for the RXM4 andor

RXM56 Register as appropriate Note that validation check-

ing of the ‘‘act’’ and ‘‘dea’’ bits during activationdeactiva-

tion is not affected by OB1OB0

OB1

OB0

Interrupt every superframe (no checking)

Interrupt if any bit changed from previous

superframe

2 consecutive times for same new bit(s)

before Interrupt

3 consecutive times for same new bit(s)

before Interrupt

Receive Embedded Operations Channel Interrupt

Enable OC1 OC0

These bits determine how many consecutive half-super-

frames must be received with the same new address or data

in the Embedded Operations Channel before an Interrupt is

generated for the RX EOC Register

OC1

OC0

Interrupt every received eoc message (no

checking)

Interrupt every received eoc message

which differs from previous message

2 consecutive times for same new message

before Interrupt

3 consecutive times for same new message

before Interrupt

911 Transmit M4 Channel Register TXM4

(Write Only)

When the line is superframe synchronized the device trans-

mits the contents of this register to the line in the M4 over-

head bit field once per superframe

Byte 2

543210

ACT

M42

M43

M44

M45

M46

M47

M48

At Power-On Reset and each time the device is Deactivat-

ed (or an Activation attempt fails) this register is initialized

to X 7F

ACT Bit

The ACT bit in the TXM4 register does not normally control

the ‘‘act’’ bit in the M4 word transmitted to the line (see

Table I) That ‘‘act ’’ bit is generated automatically within the

device and can be controlled through the Activation Control

tion) In normal operation the ACT bit in the TXM4 register is

ignored

M42 – M48 Bits

As shown in the Frame Formats in Table I the functions of

these bits depend on the mode of the device They should

be programmed as appropriate prior to an Activation Re-

quest with the exception of the M42 bit in LT Mode This is

the dea bit which is automatically controlled by the device

in response to AR and DR commands the M42 bit in this

TP3410 Datasheet(PDF) 20 Page - National Semiconductor (TI)

TP3410 Datasheet(HTML) 20 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL