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TP3410 Datasheet(PDF) 24 Page - National Semiconductor (TI) |
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TP3410 Datasheet(HTML) 24 Page - National Semiconductor (TI) |
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24 / 32 page ![]() Functional Description (Continued) Deactivation is initiated by writing the DR command in the Activation Control Register causing ‘‘dea’’e0 to be trans- mitted towards the NT When the NT ceases to transmit confirmation of deactivation is provided by a DI Status indi- cator 117 NT Mode ActivationDeactivation If activation is initiated by the upstream (LT mode) end with the NT either powered up or down a Line Signal Detect Interrupt will be generated on detection of the 10 kHz ‘‘wake-up’’ tone The Activation Indication Register will show this condition and if the device is powered down the LSD pin will be pulled low To proceed with the activation sequence all registers must be programmed appropriately (see Note 1) and the device must then be powered up The use of the commands and status indicators is the same whether activation is initiated locally or in response to the Line Signal Detect Interrupt An AR command will enable the device to automatically proceed with the activation se- quence An internal 15s default timer is also started (in North America the timer value should be 15 seconds if a single DSL section is being activated) See TP3410 User’s Manual for additional information on activation and deacti- vation The sequence continues until the NT acquires superframe synchronization on the SL2 signal received from the LT At this point an AP Interrupt is generated and the device starts transmitting SN3 with ‘‘act’’ e 0 To complete activation normally when the NT has detected INFO3 signals from a TE the ‘‘act’’ bit must be set e 1 by writing the AC com- mand to the Activation Control Register An AI Status indi- cation will finally be generated by the device when the loop is fully synchronized and receiving SL3 frames with ‘‘act’’e1 this is automatically validated 3 times regardless of the options selected in Register OPR The loop is then fully activated with all channels in the data stream available for use If activation is not successfully completed before expiry of the 15s timer the device generates an EI followed by a DI fault indication and ensures that the Activation Sequencer returns to the Full Reset state prior to any re-attempt to activate Deactivation is normally initiated by the LT which sets ‘‘dea’’e0 towards the NT The TP3410 in NT mode will detect and validate this bit 3 times prior to setting the DP interrupt (regardless of the options selected in OPR) Trans- mission will cease when it is detected that the far-end signal has ceased after which the device enters the Reset state and generates a DI Interrupt to indicate that deactivation is complete Note 1 The M45 bit conveys an indication of whether the NT can support a warm-start procedure (the ‘‘cso’’ bit) Since the TP3410 automati- cally supports both cold and warm start set ‘‘cso’’e0 Applications Information LINE INTERFACE CIRCUIT The transmission performance obtainable from a TP3410 U-interface is strongly dependent on the line interface circuit (LIC) design Two designs shown in Figures 9 and 10 are recommended They should be adhered to strictly The channel response and insertion losses of these circuits have been carefully designed as an integral part of the over- all signal processing system to ensure the performance re- quirements are met under all specified loop conditions De- viations from these designs may result in sub-optimal per- formance or even total failure of the system to operate on some types of loops The standare LIC (Figure 9) has the advantage of back- wards compatibility with Rev 2x devices together with a generally lower component sensitivity The TP3410 must be configured to select the chosen LIC For the standard LIC set saif e 1 in register CR4 This is the default configura- tion The alternative LIC (Figure 10) does not use lineside surge limiting resistors and so has advantages where line power- ing is required To configure the TP3410 for the alternative LIC set saif e 0 Transformer parameters form a major part of the LIC Two of the most important are Turns Ratio Chip side (primary) Line side (secondary) e 115 Secondary inductance LS e 27 mH g5% at 1 kHz For more details on transformer specification and for a list of qualified vendors see the TP3410 User’s Manual AN-913 BOARD LAYOUT While the pins of the TP3410 are well protected against electrical misuse it is recommended that the standard CMOS practice of applying GND to the device before any other connections are made should always be followed In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present an extra long ground pin on the connector should be used Great care must be taken in the layout of the printed circuit board in order to preserve the high transmission perform- ance of the TP3410 To maximize performance do not use the philosophy of separating analog and digital grounds on the board The 3 GND pins should be connected together as close as possible to the pins and the 2 VCC pins should be strapped together All ground connections to each de- vice should meet at a common point as close as possible to the 3 GND pins in order to prevent the interaction of ground return currents flowing through a common bus impedance A decoupling capacitor of 01 mF should be connected from this common point to the VCC pins Taking care with the pcb layout in the following ways will also help prevent noise in- jection into the receiver front-end and maximize the trans- mission performance 1 Keep the crystal oscillator components away from the receiver inputs and use a ground plane for shielding around these components 2 Keep the connections between the device and the com- ponents on the Lig inputs short 3 Keep the connections between the device and trans- former short ADDITIONAL INFORMATION For more in-depth information on a variety of applications the TP3410 Users Manual AN-913 is a comprehensive guide to the hardware and software required to meet the ANSI interface specification 24 |
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