HPC46100 datasheet(22/32 Pages) NSC

22 / 32 page

Timer Overview (Continued)

the timer and operation will continue as in the PWM mode

Alternately an interrupt from the RnB load can be used to

branch to a routine that would set the timer into mode 3

waiting for the trigger for another pulse

Figure 25 shows a

block diagram of the timer in this mode

TLDD11289 – 27

FIGURE 25 Port OutputExternally Triggered PWM

WATCHDOG LOGIC

The WATCHDOG Logic monitors the operations taking

place and signals upon the occurrence of any illegal activity

The illegal conditions that trigger the WATCHDOG logic are

potentially infinite loops Should the WATCHDOG register

not be written to before Timer T0 overflows twice or more

often than once every 4096 counts an infinite loop condi-

tion is assumed to have occurred Any illegal condition

forces the WATCHDOG Output (WO) pin low The WO pin is

an open drain output and can be connected to the RESET

or NMI inputs or to the users external logic

MICROWIREPLUS

MICROWIREPLUS is used for synchronous serial data

communications and has an 8-bit parallel-loaded serial shift

the clock for the serial shift register (SIO) The SK clock

signal can be provided by an internal or external source

The internal clock rate is programmable by the DIVBY regis-

ter A DONE flag indicates when the data shift is completed

The MICROWIREPLUS capability enables it to interface

with any of National Semiconductor’s MICROWIRE periph-

erals (ie AD converters display drivers EEPROMs)

MICROWIREPLUS OPERATION

The HPC46100 can enter the MICROWIREPLUS mode as

the master or a slave A control bit in the IRCD register

determines whether the HPC46100 is the master or slave

The shift clock is generated when the HPC46100 is config-

ured as a master An externally generated shift clock on the

SK pin is used when the HPC46100 is configured as a slave

When the HPC46100 is a master the DIVBY register pro-

grams the frequency of the SK clock The DIVBY register

allows the SK clock frequency to be programmed in 15 se-

lectable steps from 64 Hz to 1 MHz with CKI at 160 MHz

The contents of the SIO register may be accessed through

any of the memory access instructions Data waiting to be

transmitted in the SIO register is clocked out on the falling

edge of the SK clock Serial data on the SI pin is clocked in

on the rising edge of the SK clock

TLDD11289 – 28

FIGURE 26 MICROWIREPLUS

HPC46100 UART

The HPC46100 contains a software programmable UART

The UART (see

Figure 27 ) consists of a transmit shift regis-

ter a receiver shift register and five addressable registers

as follows a transmit buffer register (TBUF) a receiver buff-

er register (RBUF) a UART control and status register

(ENU) a UART receive control and status register (ENUR)

and a UART interrupt and clock source register (ENUI) The

ENU register contains flags for transmit and receive func-

tions this register also determines the length of the data

frame (7 8 or 9 bits) and the value of the ninth bit in trans-

mission The ENUR register flags framing parity and data

overrun errors while the UART is receiving Other functions

of the ENUR register include saving the ninth bit received in

the data frame reporting receiving and transmitting status

and enabling or disabling the UART’s Attention Mode of

operation

The determination of an internal or external clock source is

done by the ENUI register as well as selecting the number

of stop bits (

1 1

or 2 stop bits) selecting between the

synchronous or asynchronous mode and enabling or dis-

abling transmit and receive interrupts The clock inputs to

the Transmitter and Receiver sections of the UART can be

individually selected to come from either an off-chip source

on the CKX pin or one of the two on-chip sources The

Divide-By (DIVBY) Register provides upward compatibility

from earlier HPC family members and the most flexible and

accurate on-chip clocking is provided by the Baud Rate

Generator (BRG)

HPC46100 Datasheet(PDF) 22 Page - National Semiconductor (TI)

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