HPC46100 datasheet(19/32 Pages) NSC

19 / 32 page

Chip Select Signals (Continued)

The Chip Select Address Range Selection (SEL) defines the

address range the chip select is valid over For Chip Select

0 (CSC0) the address range starts at location 0800 hex and

extends to S0FFF hex where S0 is the 4-bit contents of the

SEL field For both Chip Select 1 (CSC1) and Chip Select 2

(CSC2) the SEL field defines a single 4 kbyte range S1000

through S1FFF for CSC1 and S2000 through S2FFF for

CSC2 where S1 and S2 are their respective SEL field con-

tents These ranges can be used to control peripherals by

using the ‘‘Slow Peripheral’’ bus timing mode Chip Select 3

(CSC3) defines a range beginning at S3000 hex and contin-

uing through FFFF hex This range will typically define the

off-chip ROM space See

Figure 18

FFFF

9000

w S3 e 9

7FFF

w S2 e 7

7000

5FFF

w S1 e 5

5000

2FFF

w S0 e 2

0800

(On-Chip)

0000

Shaded Ranges Present

No Chip Select and

Global Bus Features

are Selected

FIGURE 18 Chip Select Address Ranges

Chip Select 0 and Chip Select 3 can be programmed inde-

pendently to operate with 1 2 or 4 wait states Chip Select 1

and 2 can be programmed independently to operate in na-

tive bus mode with 1 2 or 4 wait states or slow peripheral

bus mode

Timer Overview

The HPC46100 contains seven 16-bit timers four core tim-

ers and three high speed timers Timers T0 – T3 are the

standard core timers and are fully compatible with the core

timers on other HPC family members See

Figure 19 and

Figure 20

TLDD11289 – 21

FIGURE 19 Timers T0 – T1 Block

TLDD11289 – 22

FIGURE 20 Timers T2 – T3 Block

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