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HPC46100 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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HPC46100 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 32 page  TLDD11289 PRELIMINARY June 1994 HPC46100 High-Performance microController with DSP Capability General Description The HPC46100 is a member of the HPCTM family of High Performance microControllers Each member of the family has a similar core CPU with unique memory resources and IO configuration to suit specific applications The HPC46100 is fabricated in National’s advanced microCMOS technology This process combined with an advanced archi- tecture provides fast flexible IO control efficient data ma- nipulation high speed computation and low power con- sumption Throughput is enhanced by operating the HPC46100 at fre- quencies up to 40 MHz by integrating a MultiplyAccumu- late Unit (MAU) onto the chip and by optimizing instructions to increase efficiency These features increase performance in closed loop digital servo and filter applications The HPC devices are complete microcomputers on a single chip All system timing internal logic RAM and IO are provided on the chip to produce a cost effective solution for high performance applications On-chip functions such as an MAU unit PWM outputs Chip Select Signals UART up to seven 16-bit timers with input capture capability WATCHDOGTM logic vectored interrupts and MICROWIREPLUSTM provide a high level of system inte- gration The ability to directly address up to 64 kbytes of memory enables the HPC to be used in powerful applica- tions typically performed by microprocessors and peripheral chips (Continued) Features Y MultiplyAccumulate Unit for fast signed multiply or mul- tiply-accumulate Y High speed 16 bit timers with PWM outputs or input capture logic Y 4 Chip select output logic with programmable control Y 8-channel 8-bit AD Converter Y 1024 bytes of on-chip 0 wait state RAM Y FAST 100 ns for fastest instruction when using 400 MHz clock Y Very low power with two power save modes IDLE and HALT Y UART full duplex with a programmable baud rate gen- erator and parity checkingdetection Y MICROWIREPLUS serial IO interface Y 8 vectored interrupt sources Y Signed overflow flag for add and subtract instructions Y 16 x 16 multiply and 32 x 16 divide Y 16-bit architecture with byte and word operations Y 64 kbytes of direct memory addressing Y 8- or 16-bit wide external memory Y Program instructions can be executed from RAM Y Up to 31 general purpose IO lines that are memory mapped Y WATCHDOG logic Block Diagram TLDD11289 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation HPCTM WATCHDOGTM MICROWIREPLUSTM and MICROWIRETM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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