HPC46100 datasheet(17/32 Pages) NSC

17 / 32 page

HPC46100 Interrupts (Continued)

TLDD11289 – 18

FIGURE 15 Interrupt Enable Logic

MultiplyAccumulate Unit (MAU)

This is dedicated hardware that is supported by instructions

which perform basic multiply-accumulate DSP steps for FIR

and IIR filter calculations an arithmetic right shift of the

Math unit Result Register (MRR) and a signed multiply of

two 16-bit values producing a 32-bit result

The MACZ and MAC instructions support the MAU by fetch-

ing data and performing circular buffer management in par-

allel with the multiplication The MACZ instruction is used

initially and it is followed by a string of additional MAC in-

structions

one instruction per filter tap (including the

MACZ) The source values are taken as 16-bit values there

is not a form that operates on byte-wide inputs The MACZ

instruction clears the result register before completing the

first multiply operation

The MAC instruction is opcode 38 hex The MACZ instruc-

tion is opcode 39 hex Both instructions are one byte in

length and neither allows use of an Addressing Directive

prefix

The specific function performed is as follows

Clear MRR to zero (MACZ instruction only)

Fetch 16-bit data pointed to by B and issue it to the

MAU as the first operand

Increment B by two (bytes)

compare B with K

B l K then load B from A

Fetch 16-bit data pointed to by X increment X by two

(bytes)

Issue data to the MAU to start multiply-accumulate op-

eration The MAU multiplies the two operands issued to

it and adds the 32-bit result to the current 32-bit con-

tents of the MRR register

On completion the result goes to the MRR register The

MVP bit in the PSW is set to a ‘‘1’’ if a signed (2’s comple-

ment) overflow occurred in the positive direction as a result

of the accumulation substep (overflow from the multiplica-

tion substep is impossible) If the overflow occurred in the

negative direction the MVN bit is set instead Neither of

these bits is affected by the MAU if the other is already set

By stringing together a sequence of MAC instructions the

HPC46100 can do a multiply-accumulate every 9 cycles (as-

suming a 1 wait state instruction fetch) At 40 MHz this

gives a 450 ns multiply-accumulate (including data fetching

and circular buffer management) This can be reduced to

400 ns if executed from internal RAM

Chip Select Signals

CHIP SELECT LOGIC

The chip select logic can produce up to four chip select

signals without any off-chip logic The chip select logic sup-

ports two bus timing modes The first bus timing mode is

native bus mode which is the standard bus mode of all HPC

family members The second bus mode is the slow peripher-

al bus mode which allows the HPC46100 to interface with

slow peripherals without external chip select logic There is

an additional data strobe provided for auxiliary bus timing

This auxiliary strobe is called the E signal

Each of chip select signals is controlled by a dedicated chip

select control register (CSC0 – CSC3) The control registers

contain one bit to enabledisable the chip select signals

one bit to select the polarity of the chip select signal two

bits program the wait states of the data accesses four bits

that select the address range which the chip select signals

are active in and one bit to enable or disable the E signal

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