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HPC46100 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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HPC46100 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 32 page  40 MHz (Continued) AC Electrical Characteristics (Continued) See Notes 1 and 4 and Figure 1 thru Figure 5 ) VCC e 50V g10% unless otherwise specified TA e 25 C one wait state Symbol Parameter Min Max Units EXTERNAL HOLD tSALE e 075 tC a 40 HLD Falling Edge before ALE Rising Edge 775 ns tHWP e 075 tC a 35 HLD Pulse Width 725 ns tHAE e 075 tC a 100 HLDA Falling Edge after HLD Falling Edge (Note 3) 1375 ns tHAD e 075 tC a 85 HLDA Rising Edge after HLD Rising Edge 1225 ns tBF Bus TRI-Stated after HLDA Falling Edge (Note 5) 70 ns tBE e 075 tC a 30 Bus Enable after HLDA Rising Edge 675 ns NATIVE BUS TIMING ADDRESS CYCLE tLL e 05 tC b10 ALE Pulse Width 15 ns t1ALR ALE Rising Edge after CK1 Rising Edge (Note 2) 0 35 ns t1ALF ALE Falling Edge after CK1 Falling Edge (Note 2) 0 35 ns t2ALR e 025 tC a 20 ALE Rising Edge after CK2 Rising Edge 325 ns t2ALF e 025 tC a 20 ALE Falling Edge after CK2 Falling Edge 325 ns tST e 025 tC b 9 Address Valid to ALE Falling Edge 35 ns tVP e 05 tC b 10 Address Hold after ALE Falling Edge 15 ns READ CYCLE tRW e 025 tC a WS b 15 RD Pulse Width 475 ns tARD e 075 tC b 20 Address Valid to RD Falling Edge 175 ns tARR e 05 tC b 20 ALE Falling Edge to RD Falling Edge 5 ns tRD e 025 tC a WS b 20 RD Falling Edge to Input Data Valid 425 ns tDR Data Hold after RD Rising Edge 0 50 ns tACC e tC a WS b 20 Address Valid to Input Data Valid 80 ns WRITE CYCLE tWW e 075 tC a WS b 15 WR Pulse Width 725 ns tV e 05 tC a WS b 20 Data Valid before WR Rising Edge 55 ns tHW e 05 tC b 10 Data Hold after WR Rising Edge 15 ns tAWR e 075 tC b 20 Address Valid to WR Falling Edge 175 ns READY INPUT tRDYS RDY Falling Edge before CK2 Falling Edge 45 ns tRDYH RDY Rising Edge after CK2 Falling Edge 0 ns tRDYV e WS a 025 tC b 30 RDY Falling Edge after RD or WR Falling Edge 325 ns CHIP SELECT NATIVE BUS TIMING tCS30RD e 075 tC b 30 CS3 CS0 Valid to RD Falling Edge 75 ns tACCS30 e tC a WS b 30 CS3 CS0 Valid to Input Data Valid 70 ns tCS21RD e 075 tC b 35 CS2 CS1 Valid to RD Falling Edge 25 ns tACCS21 e tC a WS b 35 CS2 CS1 Valid to Input Data Valid 65 ns tCSHR e tC b 15 Chip Select Hold after RD Rising Edge 35 ns tCS30WR e 075 tC b 30 CS3 CS0 Valid to WR Falling Edge 75 ns tCS21WR e 075 tC b 35 CS2 CS1 Valid to WR Falling Edge 25 ns tCSHW e 05 tC b 15 Chip Select Hold after WR Rising Edge 10 ns 4 |
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