AD Converter Specifications

Parameter

Conditions

Min

Typ

Max

Units

Resolution

8

Bits

Reference Voltage Input

3

V

Absolute Accuracy

g

1

LSB

Non-Linearity

Deviation from the

g

LSB

Best Straight Line

Differential Non-Linearity

g

LSB

Input Reference Resistance

16

48

kX

Common Mode Input Range (Note 6)

AGND

V

DC Common Mode Error

g

LSB

Off Channel Leakage Current

1

m

A

On Channel Leakage Current

1

m

A

AD Clock Frequency (Note 7)

01

20

MHz

Conversion Time (Note 8)

130

AD Clock

Cycle

Note 6

input diode to conductespecially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode

Note 7

See Prescaler description

Note 8

Conversion Time includes sample and hold time See following diagrams

TLDD11289 – 33

Note

The trigger condition generated by the start conversion method selected by the SC bits requires one CK2 to propagate through before the trigger condition is

known Once the trigger condition is known the sample and hold will start at the next rising edge of ADCLK The diagram shows worst case

6